Lines Matching defs:bank
58 #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
847 static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
849 return readl(bank->base + reg);
852 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
855 writel(val, bank->base + reg);
858 static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
865 gpio_writel(bank, (0x10000 | val) << bit, reg);
868 static inline void gpio_enable(struct pistachio_gpio_bank *bank,
871 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
874 static inline void gpio_disable(struct pistachio_gpio_bank *bank,
877 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
1168 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1170 if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1178 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1181 if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1186 return !!(gpio_readl(bank, reg) & BIT(offset));
1192 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1194 gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
1200 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1202 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
1203 gpio_enable(bank, offset);
1211 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1214 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
1215 gpio_enable(bank, offset);
1222 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1224 gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1229 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1231 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1232 gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
1237 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1239 gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
1240 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1255 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1259 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1260 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1262 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1266 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1267 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1269 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1273 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1275 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1279 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1280 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1284 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1285 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1303 struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
1309 pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1310 gpio_readl(bank, GPIO_INTERRUPT_EN);
1347 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1349 seq_printf(p, "GPIO%d", bank->instance);
1365 struct pistachio_gpio_bank *bank;
1377 dev_err(pctl->dev, "No node for bank %u\n", i);
1385 "No gpio-controller property for bank %u\n", i);
1393 dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);
1398 dev_err(pctl->dev, "No IRQ for bank %u\n", i);
1404 bank = &pctl->gpio_banks[i];
1405 bank->pctl = pctl;
1406 bank->base = pctl->base + GPIO_BANK_BASE(i);
1408 bank->gpio_chip.parent = pctl->dev;
1409 bank->gpio_chip.fwnode = child;
1411 girq = &bank->gpio_chip.irq;
1426 ret = gpiochip_add_data(&bank->gpio_chip, bank);
1433 ret = gpiochip_add_pin_range(&bank->gpio_chip,
1435 bank->pin_base, bank->npins);
1439 gpiochip_remove(&bank->gpio_chip);
1447 bank = &pctl->gpio_banks[i - 1];
1448 gpiochip_remove(&bank->gpio_chip);