Lines Matching refs:port
131 u8 port;
138 addr->port = pin / priv->bitcount;
142 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
144 return bit + port * priv->bitcount;
289 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
328 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
351 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
473 if ((priv->ports & BIT(addr.port)) == 0) {
474 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
475 addr.port, addr.bit);
584 * Note that the SGIO pin is defined by *2* numbers, a port
604 const char *range_property_name = "microchip,sgpio-port-ranges";
609 /* Calculate port mask */
612 dev_err(dev, "%s port range: '%s' property\n",
631 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
657 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
661 BIT(addr.port), (!!(type & 0x1)) << addr.port);
663 BIT(addr.port), (!!(type & 0x2)) << addr.port);
667 BIT(addr.port), polarity << addr.port);
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
689 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
717 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
766 int bit, port, gpio;
776 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
777 gpio = sgpio_addr_to_pin(priv, port, bit);
843 addr.port, addr.bit);
906 int div_clock = 0, ret, port, i, nbanks;
981 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
982 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);