Lines Matching defs:data
21 /* GPIO data registers' offsets */
105 * @soc: Pin control configuration data based on SoC
131 * struct keembay_pin_soc - Pin control config data based on SoC
949 pin_mode = *(u8 *)(func->data);
1280 static void keembay_gpio_clear_irq(struct irq_data *data, unsigned long pos,
1283 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1285 unsigned long trig = irqd_get_trigger_type(data);
1362 static void keembay_gpio_irq_enable(struct irq_data *data)
1364 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1366 unsigned int trig = irqd_get_trigger_type(data);
1367 irq_hw_number_t pin = irqd_to_hwirq(data);
1383 static void keembay_gpio_irq_ack(struct irq_data *data)
1396 static void keembay_gpio_irq_disable(struct irq_data *data)
1398 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1400 irq_hw_number_t pin = irqd_to_hwirq(data);
1408 keembay_gpio_clear_irq(data, pos, src, pin);
1415 static int keembay_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1417 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1428 irq_set_handler_locked(data, handle_edge_irq);
1430 irq_set_handler_locked(data, handle_level_irq);
1593 functions[i].data);
1633 fdesc->data = &mux->mode;
1654 { .compatible = "intel,keembay-pinctrl", .data = &keembay_data },