Lines Matching defs:jzgc
3259 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3263 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3268 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3271 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3272 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3282 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3285 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3293 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3294 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3297 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3299 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3300 jzgc->jzpc->info->reg_offset),
3301 jzgc->gc.base / PINS_PER_GPIO_CHIP);
3304 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3315 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3318 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3321 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3326 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3329 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3330 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3331 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3332 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3334 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3337 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3366 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
3369 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3373 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3374 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3379 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3380 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3381 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3382 ingenic_gpio_shadow_set_bit_load(jzgc);
3383 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3384 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
3385 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3386 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3387 ingenic_gpio_shadow_set_bit_load(jzgc);
3389 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3390 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3397 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3400 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3401 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3403 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3409 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3412 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3413 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3415 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3421 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3426 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3427 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3428 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3429 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3431 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3439 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3444 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3445 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3446 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3447 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3449 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3457 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3462 !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3467 high = ingenic_gpio_get_value(jzgc, irq);
3469 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3471 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3474 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3475 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3476 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3477 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3479 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3485 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3502 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3508 bool high = ingenic_gpio_get_value(jzgc, irq);
3513 irq_set_type(jzgc, irq, type);
3520 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3522 return irq_set_irq_wake(jzgc->irq, on);
3528 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3534 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3535 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3536 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3537 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3539 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3549 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3551 ingenic_gpio_set_value(jzgc, offset, value);
3556 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3558 return (int) ingenic_gpio_get_value(jzgc, offset);
3643 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3644 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
4159 struct ingenic_gpio_chip *jzgc;
4171 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4172 if (!jzgc)
4175 jzgc->jzpc = jzpc;
4176 jzgc->reg_base = bank * jzpc->info->reg_offset;
4178 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4179 if (!jzgc->gc.label)
4186 jzgc->gc.base = bank * 32;
4188 jzgc->gc.ngpio = 32;
4189 jzgc->gc.parent = dev;
4190 jzgc->gc.fwnode = fwnode;
4191 jzgc->gc.owner = THIS_MODULE;
4193 jzgc->gc.set = ingenic_gpio_set;
4194 jzgc->gc.get = ingenic_gpio_get;
4195 jzgc->gc.direction_input = ingenic_gpio_direction_input;
4196 jzgc->gc.direction_output = ingenic_gpio_direction_output;
4197 jzgc->gc.get_direction = ingenic_gpio_get_direction;
4198 jzgc->gc.request = gpiochip_generic_request;
4199 jzgc->gc.free = gpiochip_generic_free;
4206 jzgc->irq = err;
4208 girq = &jzgc->gc.irq;
4217 girq->parents[0] = jzgc->irq;
4221 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);