Lines Matching defs:bank
34 * designed the pin id into this bank.
82 * @last_bank_count: number of lines in the last bank (can be less than
101 unsigned int bank;
115 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
121 * @irqs: table containing the hw irq number of the bank. The index of the
122 * table is the bank id.
162 unsigned int bank, unsigned int reg)
165 + ATMEL_PIO_BANK_OFFSET * bank + reg);
169 unsigned int bank, unsigned int reg,
173 + ATMEL_PIO_BANK_OFFSET * bank + reg);
190 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
192 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
221 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
231 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
240 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
247 int bank = ATMEL_PIO_BANK(d->hwirq);
250 /* The gpio controller has one interrupt line per bank. */
251 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
254 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
256 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
283 int n, bank = -1;
285 /* Find from which bank is the irq received. */
288 bank = n;
293 if (bank < 0) {
295 "no bank associated to irq %u\n", irq);
302 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
304 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
312 bank * ATMEL_PIO_NPINS_PER_BANK + n));
325 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
327 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
329 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
340 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
349 unsigned int bank;
353 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
354 unsigned int word = bank;
359 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
360 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
365 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
380 atmel_gpio_write(atmel_pioctrl, pin->bank,
384 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
386 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
388 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
398 atmel_gpio_write(atmel_pioctrl, pin->bank,
407 unsigned int bank;
409 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
411 unsigned int word = bank;
418 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
424 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
427 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
452 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
455 + bank * ATMEL_PIO_BANK_OFFSET;
468 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
471 + bank * ATMEL_PIO_BANK_OFFSET;
804 unsigned int bank, pin, pin_id = grp->pin;
864 bank = ATMEL_PIO_BANK(pin_id);
870 bank * ATMEL_PIO_BANK_OFFSET +
874 bank * ATMEL_PIO_BANK_OFFSET +
997 * For each bank, save IMR to restore it later and disable all GPIO
1100 /* if last bank has limited number of pins, adjust accordingly */
1146 unsigned int bank = ATMEL_PIO_BANK(i);
1155 atmel_pioctrl->pins[i]->bank = bank;
1161 bank + 'A', line);
1168 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1199 /* There is one controller but each bank has its own irq line. */
1209 dev_dbg(dev, "bank %i: irq=%d\n", i, ret);