Lines Matching defs:gpio
6 #include <linux/gpio/driver.h>
136 seq_printf(s, "-- module %d [gpio%d - %d]\n",
244 unsigned int gpio = BIT(irqd_to_hwirq(d));
246 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
251 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
252 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
256 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
257 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
261 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
265 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
269 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
277 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
281 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
292 unsigned int gpio = irqd_to_hwirq(d);
294 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
295 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
303 unsigned int gpio = irqd_to_hwirq(d);
306 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
307 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
308 gpiochip_disable_irq(gc, gpio);
316 unsigned int gpio = irqd_to_hwirq(d);
319 gpiochip_enable_irq(gc, gpio);
320 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
321 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
327 unsigned int gpio = irqd_to_hwirq(d);
330 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
331 npcmgpio_direction_input(gc, gpio);
645 /* add placeholder for none/gpio */
647 NPCM7XX_GRP(gpio),
1028 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
1097 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
1098 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
1099 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
1100 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1101 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1102 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1103 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1104 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
1126 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1141 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
1142 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
1143 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
1144 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
1451 int gpio = (pin % bank->gc.ngpio);
1452 unsigned long pinmask = BIT(gpio);
1471 int gpio = BIT(pin % bank->gc.ngpio);
1477 gpio);
1481 gpio);
1513 int gpio = (pin % bank->gc.ngpio);
1514 unsigned long pinmask = BIT(gpio);
1539 int gpio = BIT(pin % bank->gc.ngpio);
1547 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1552 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1698 int gpio = BIT(offset % bank->gc.ngpio);
1703 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1705 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1728 int gpio = (pin % bank->gc.ngpio);
1729 unsigned long pinmask = BIT(gpio);
1791 int gpio = BIT(pin % bank->gc.ngpio);
1796 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1800 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1801 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1804 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1805 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1808 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1812 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1816 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1819 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1822 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
1902 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
1904 dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);
2011 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
2024 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);