Lines Matching refs:nmk_chip
289 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
294 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
295 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
300 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
301 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
304 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
309 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
314 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
317 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
322 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
325 nmk_chip->pull_up &= ~BIT(offset);
330 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
333 nmk_chip->pull_up |= BIT(offset);
334 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
336 nmk_chip->pull_up &= ~BIT(offset);
337 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
341 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
344 bool enabled = nmk_chip->lowemi & BIT(offset);
350 nmk_chip->lowemi |= BIT(offset);
352 nmk_chip->lowemi &= ~BIT(offset);
354 writel_relaxed(nmk_chip->lowemi,
355 nmk_chip->addr + NMK_GPIO_LOWEMI);
358 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
361 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
364 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
368 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
370 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
373 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
376 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
377 __nmk_gpio_set_output(nmk_chip, offset, val);
380 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
384 u32 rwimsc = nmk_chip->rwimsc;
385 u32 fwimsc = nmk_chip->fwimsc;
387 if (glitch && nmk_chip->set_ioforce) {
391 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
392 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
394 nmk_chip->set_ioforce(true);
397 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
399 if (glitch && nmk_chip->set_ioforce) {
400 nmk_chip->set_ioforce(false);
402 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
403 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
408 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
410 u32 falling = nmk_chip->fimsc & BIT(offset);
411 u32 rising = nmk_chip->rimsc & BIT(offset);
412 int gpio = nmk_chip->chip.base + offset;
413 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
423 nmk_chip->rimsc &= ~BIT(offset);
424 writel_relaxed(nmk_chip->rimsc,
425 nmk_chip->addr + NMK_GPIO_RIMSC);
429 nmk_chip->fimsc &= ~BIT(offset);
430 writel_relaxed(nmk_chip->fimsc,
431 nmk_chip->addr + NMK_GPIO_FIMSC);
434 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
615 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
617 clk_enable(nmk_chip->clk);
618 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
619 clk_disable(nmk_chip->clk);
627 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
639 rimscval = &nmk_chip->rimsc;
640 fimscval = &nmk_chip->fimsc;
644 rimscval = &nmk_chip->rwimsc;
645 fimscval = &nmk_chip->fwimsc;
649 if (nmk_chip->edge_rising & BIT(offset)) {
654 writel(*rimscval, nmk_chip->addr + rimscreg);
656 if (nmk_chip->edge_falling & BIT(offset)) {
661 writel(*fimscval, nmk_chip->addr + fimscreg);
665 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
673 if (nmk_chip->sleepmode && on) {
674 __nmk_gpio_set_slpm(nmk_chip, offset,
678 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
681 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
686 clk_enable(nmk_chip->clk);
688 spin_lock(&nmk_chip->lock);
690 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
692 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
693 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
695 spin_unlock(&nmk_chip->lock);
697 clk_disable(nmk_chip->clk);
703 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
705 nmk_gpio_irq_maskunmask(nmk_chip, d, false);
712 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
715 nmk_gpio_irq_maskunmask(nmk_chip, d, true);
721 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
724 clk_enable(nmk_chip->clk);
726 spin_lock(&nmk_chip->lock);
729 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
732 nmk_chip->real_wake |= BIT(d->hwirq);
734 nmk_chip->real_wake &= ~BIT(d->hwirq);
736 spin_unlock(&nmk_chip->lock);
738 clk_disable(nmk_chip->clk);
746 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
756 clk_enable(nmk_chip->clk);
757 spin_lock_irqsave(&nmk_chip->lock, flags);
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
765 nmk_chip->edge_rising &= ~BIT(d->hwirq);
767 nmk_chip->edge_rising |= BIT(d->hwirq);
769 nmk_chip->edge_falling &= ~BIT(d->hwirq);
771 nmk_chip->edge_falling |= BIT(d->hwirq);
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
779 spin_unlock_irqrestore(&nmk_chip->lock, flags);
780 clk_disable(nmk_chip->clk);
788 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
790 clk_enable(nmk_chip->clk);
798 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
801 clk_disable(nmk_chip->clk);
808 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
813 clk_enable(nmk_chip->clk);
814 status = readl(nmk_chip->addr + NMK_GPIO_IS);
815 clk_disable(nmk_chip->clk);
831 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
834 clk_enable(nmk_chip->clk);
836 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
838 clk_disable(nmk_chip->clk);
848 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
850 clk_enable(nmk_chip->clk);
852 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
854 clk_disable(nmk_chip->clk);
861 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
864 clk_enable(nmk_chip->clk);
866 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
868 clk_disable(nmk_chip->clk);
876 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
878 clk_enable(nmk_chip->clk);
880 __nmk_gpio_set_output(nmk_chip, offset, val);
882 clk_disable(nmk_chip->clk);
888 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
890 clk_enable(nmk_chip->clk);
892 __nmk_gpio_make_output(nmk_chip, offset, val);
894 clk_disable(nmk_chip->clk);
900 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
904 clk_enable(nmk_chip->clk);
906 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
907 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
909 clk_disable(nmk_chip->clk);
919 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
935 clk_enable(nmk_chip->clk);
936 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
937 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
938 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
939 mode = nmk_gpio_get_mode(nmk_chip, offset);
975 if (nmk_chip->edge_rising & BIT(offset))
977 else if (nmk_chip->edge_falling & BIT(offset))
982 wake = !!(nmk_chip->real_wake & BIT(offset));
988 clk_disable(nmk_chip->clk);
1021 struct nmk_gpio_chip *nmk_chip;
1041 nmk_chip = nmk_gpio_chips[id];
1042 if (nmk_chip) {
1044 return nmk_chip;
1047 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1048 if (!nmk_chip) {
1053 nmk_chip->bank = id;
1054 chip = &nmk_chip->chip;
1066 nmk_chip->addr = base;
1074 nmk_chip->clk = clk;
1076 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1077 nmk_gpio_chips[id] = nmk_chip;
1078 return nmk_chip;
1084 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
1086 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
1106 struct nmk_gpio_chip *nmk_chip;
1113 nmk_chip = nmk_gpio_populate_chip(np, dev);
1114 if (IS_ERR(nmk_chip)) {
1116 return PTR_ERR(nmk_chip);
1123 dev->id = nmk_chip->bank;
1130 * The virt address in nmk_chip->addr is in the nomadik register space,
1133 nmk_chip->sleepmode = supports_sleepmode;
1134 spin_lock_init(&nmk_chip->lock);
1136 chip = &nmk_chip->chip;
1162 clk_enable(nmk_chip->clk);
1163 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1164 clk_disable(nmk_chip->clk);
1166 ret = gpiochip_add_data(chip, nmk_chip);
1170 platform_set_drvdata(dev, nmk_chip);
1550 * nmk_chip we're using that as backup)
1584 struct nmk_gpio_chip *nmk_chip;
1587 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]);
1588 if (!nmk_chip) {
1596 clk_enable(nmk_chip->clk);
1605 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1607 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1609 clk_disable(nmk_chip->clk);
1641 struct nmk_gpio_chip *nmk_chip;
1654 nmk_chip = gpiochip_get_data(chip);
1658 clk_enable(nmk_chip->clk);
1661 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1662 clk_disable(nmk_chip->clk);
1708 struct nmk_gpio_chip *nmk_chip;
1714 nmk_chip = find_nmk_gpio_from_pin(pin);
1715 if (!nmk_chip) {
1755 dev_dbg(nmk_chip->chip.parent,
1764 dev_dbg(nmk_chip->chip.parent,
1771 clk_enable(nmk_chip->clk);
1775 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1777 __nmk_gpio_make_output(nmk_chip, bit, val);
1779 __nmk_gpio_make_input(nmk_chip, bit);
1780 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1783 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1785 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1786 clk_disable(nmk_chip->clk);
1874 struct nmk_gpio_chip *nmk_chip;
1881 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1882 if (IS_ERR(nmk_chip))