Lines Matching refs:base
42 * @base: pinctrl register base address
53 void __iomem *base;
58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
62 reg_val = readl_relaxed(base);
66 writel_relaxed(reg_val, base);
74 tmp = readl_relaxed(pctrl->base + reg);
88 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
208 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
520 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
524 val = readl_relaxed(base);
531 writel_relaxed(val, base);
545 gpio_base = pctrl->base + port->offset;
569 gpio_base = pctrl->base + port->offset;
592 gpio_base = pctrl->base + port->offset;
612 gpio_base = pctrl->base + port->offset;
630 gpio_base = pctrl->base + port->offset;
652 gpio_base = pctrl->base + port->offset;
708 gpio_base = pctrl->base + port->offset;
736 gpio_base = pctrl->base + port->offset;
770 gpio_base = pctrl->base + port->offset;
810 gpio_base = pctrl->base + port->offset;
852 void __iomem *base;
860 base = pctrl->base + port->offset;
866 pending_irq = readl_relaxed(base + port->intc_pd);
872 owl_gpio_update_reg(base + port->intc_pd, pin, true);
889 chip->base = -1;
937 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
938 if (IS_ERR(pctrl->base))
939 return PTR_ERR(pctrl->base);