Lines Matching defs:rate
138 unsigned long rate;
301 unsigned long rate;
304 rate = clk_get_rate(phy->sys_clk);
306 for (; dpll_map->rate; dpll_map++) {
307 if (rate == dpll_map->rate)
311 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
340 unsigned long rate;
349 rate = clk_get_rate(phy->sys_clk);
350 if (!rate) {
351 dev_err(phy->dev, "Invalid clock rate\n");
354 rate = rate / 1000000;
356 val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;