Lines Matching refs:regmap_field
210 struct regmap_field *field;
219 struct regmap_field *field;
240 struct regmap_field *phy_en_refclk;
360 struct regmap_field *por_en;
361 struct regmap_field *phy_reset_n;
362 struct regmap_field *phy_en_refclk;
363 struct regmap_field *p_enable[WIZ_MAX_LANES];
364 struct regmap_field *p_align[WIZ_MAX_LANES];
365 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
366 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
367 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
368 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
369 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
370 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
371 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
372 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
373 struct regmap_field *pma_cmn_refclk_int_mode;
374 struct regmap_field *pma_cmn_refclk1_int_mode;
375 struct regmap_field *pma_cmn_refclk_mode;
376 struct regmap_field *pma_cmn_refclk_dig_div;
377 struct regmap_field *pma_cmn_refclk1_dig_div;
378 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
379 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
380 struct regmap_field *typec_ln10_swap;
381 struct regmap_field *typec_ln23_swap;
382 struct regmap_field *sup_legacy_clk_override;
709 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
719 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
727 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
786 struct regmap_field *field = mux->field;
796 struct regmap_field *field = mux->field;
809 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
871 struct regmap_field *field, const u32 *table)
929 struct regmap_field *field = div->field;
949 struct regmap_field *field = div->field;
966 struct regmap_field *field,