Lines Matching refs:init
529 dev_err(dev, "POR_EN reg field init failed\n");
536 dev_err(dev, "PHY_RESET_N reg field init failed\n");
543 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
550 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
557 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
566 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
576 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
584 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
591 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
598 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
606 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
615 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
622 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
629 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
637 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
644 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
650 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
656 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
662 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
669 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
677 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
686 dev_err(dev, "LN10_SWAP reg field init failed\n");
693 dev_err(dev, "LN23_SWAP reg field init failed\n");
699 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
745 struct clk_init_data *init;
754 init = &wiz_phy_en_refclk->clk_data;
756 init->ops = &wiz_phy_en_refclk_ops;
757 init->flags = 0;
766 init->name = clk_name;
769 wiz_phy_en_refclk->hw.init = init;
813 struct clk_init_data *init;
844 init = &mux->clk_data;
846 init->ops = &wiz_clk_mux_ops;
847 init->flags = CLK_SET_RATE_NO_REPARENT;
848 init->parent_names = parent_names;
849 init->num_parents = num_parents;
850 init->name = clk_name;
854 mux->hw.init = init;
874 struct clk_init_data *init;
902 init = &mux->clk_data;
904 init->ops = &wiz_clk_mux_ops;
905 init->flags = CLK_SET_RATE_NO_REPARENT;
906 init->parent_names = parent_names;
907 init->num_parents = num_parents;
908 init->name = clk_name;
912 mux->hw.init = init;
971 struct clk_init_data *init;
990 init = &div->clk_data;
992 init->ops = &wiz_clk_div_ops;
993 init->flags = 0;
994 init->parent_names = parent_names;
995 init->num_parents = 1;
996 init->name = clk_name;
1000 div->hw.init = init;