Lines Matching defs:wiz
353 struct wiz {
398 static int wiz_reset(struct wiz *wiz)
402 ret = regmap_field_write(wiz->por_en, 0x1);
408 ret = regmap_field_write(wiz->por_en, 0x0);
415 static int wiz_p_mac_div_sel(struct wiz *wiz)
417 u32 num_lanes = wiz->num_lanes;
422 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
423 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
424 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
425 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
429 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
438 static int wiz_mode_select(struct wiz *wiz)
440 u32 num_lanes = wiz->num_lanes;
446 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) {
448 } else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
450 } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
451 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
452 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
453 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
459 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
467 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
469 u32 num_lanes = wiz->num_lanes;
474 ret = regmap_field_write(wiz->p_align[i], enable);
478 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
486 static int wiz_init(struct wiz *wiz)
488 struct device *dev = wiz->dev;
491 ret = wiz_reset(wiz);
497 ret = wiz_mode_select(wiz);
503 ret = wiz_p_mac_div_sel(wiz);
509 ret = wiz_init_raw_interface(wiz, true);
518 static int wiz_regfield_init(struct wiz *wiz)
520 struct regmap *regmap = wiz->regmap;
521 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
522 int num_lanes = wiz->num_lanes;
523 struct device *dev = wiz->dev;
524 const struct wiz_data *data = wiz->data;
527 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
528 if (IS_ERR(wiz->por_en)) {
530 return PTR_ERR(wiz->por_en);
533 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
535 if (IS_ERR(wiz->phy_reset_n)) {
537 return PTR_ERR(wiz->phy_reset_n);
540 wiz->pma_cmn_refclk_int_mode =
542 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
544 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
547 wiz->pma_cmn_refclk_mode =
549 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
551 return PTR_ERR(wiz->pma_cmn_refclk_mode);
554 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
556 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
558 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
562 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
565 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
567 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
571 if (wiz->scm_regmap) {
572 scm_regmap = wiz->scm_regmap;
573 wiz->sup_legacy_clk_override =
575 if (IS_ERR(wiz->sup_legacy_clk_override)) {
577 return PTR_ERR(wiz->sup_legacy_clk_override);
581 wiz->mux_sel_field[PLL0_REFCLK] =
583 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
585 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
588 wiz->mux_sel_field[PLL1_REFCLK] =
590 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
592 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
595 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
597 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
599 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
603 wiz->pma_cmn_refclk1_int_mode =
605 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
607 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
612 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
614 if (IS_ERR(wiz->p_enable[i])) {
616 return PTR_ERR(wiz->p_enable[i]);
619 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
621 if (IS_ERR(wiz->p_align[i])) {
623 return PTR_ERR(wiz->p_align[i]);
626 wiz->p_raw_auto_start[i] =
628 if (IS_ERR(wiz->p_raw_auto_start[i])) {
631 return PTR_ERR(wiz->p_raw_auto_start[i]);
634 wiz->p_standard_mode[i] =
636 if (IS_ERR(wiz->p_standard_mode[i])) {
639 return PTR_ERR(wiz->p_standard_mode[i]);
642 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
643 if (IS_ERR(wiz->p0_fullrt_div[i])) {
645 return PTR_ERR(wiz->p0_fullrt_div[i]);
648 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
649 if (IS_ERR(wiz->p0_mac_src_sel[i])) {
651 return PTR_ERR(wiz->p0_mac_src_sel[i]);
654 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
655 if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
657 return PTR_ERR(wiz->p0_rxfclk_sel[i]);
660 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
661 if (IS_ERR(wiz->p0_refclk_sel[i])) {
663 return PTR_ERR(wiz->p0_refclk_sel[i]);
666 wiz->p_mac_div_sel0[i] =
668 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
671 return PTR_ERR(wiz->p_mac_div_sel0[i]);
674 wiz->p_mac_div_sel1[i] =
676 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
679 return PTR_ERR(wiz->p_mac_div_sel1[i]);
683 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
685 if (IS_ERR(wiz->typec_ln10_swap)) {
687 return PTR_ERR(wiz->typec_ln10_swap);
690 wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
692 if (IS_ERR(wiz->typec_ln23_swap)) {
694 return PTR_ERR(wiz->typec_ln23_swap);
697 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
698 if (IS_ERR(wiz->phy_en_refclk)) {
700 return PTR_ERR(wiz->phy_en_refclk);
741 static int wiz_phy_en_refclk_register(struct wiz *wiz)
744 struct device *dev = wiz->dev;
768 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
778 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
809 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
812 struct device *dev = wiz->dev;
832 clk = wiz->input_clks[mux_sel->parents[i]];
862 wiz->output_clks[clk_index] = clk;
870 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
873 struct device *dev = wiz->dev;
965 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
969 struct device *dev = wiz->dev;
1013 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
1015 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1016 struct device *dev = wiz->dev;
1020 switch (wiz->type) {
1037 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1043 of_clk_del_provider(wiz->dev->of_node);
1046 static int wiz_clock_register(struct wiz *wiz)
1048 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1049 struct device *dev = wiz->dev;
1057 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
1064 ret = wiz_phy_en_refclk_register(wiz);
1070 wiz->clk_data.clks = wiz->output_clks;
1071 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
1072 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
1079 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
1081 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1082 struct device *dev = wiz->dev;
1096 wiz->input_clks[WIZ_CORE_REFCLK] = clk;
1100 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
1102 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
1104 switch (wiz->type) {
1109 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
1112 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
1115 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
1123 if (wiz->data->pma_cmn_refclk1_int_mode) {
1130 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
1134 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
1136 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
1145 wiz->input_clks[WIZ_EXT_REFCLK] = clk;
1149 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
1151 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
1153 switch (wiz->type) {
1158 ret = wiz_clock_register(wiz);
1160 dev_err(dev, "Failed to register wiz clocks\n");
1175 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
1187 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1196 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
1210 wiz_clock_cleanup(wiz, node);
1219 struct wiz *wiz = dev_get_drvdata(dev);
1223 ret = regmap_field_write(wiz->phy_reset_n, false);
1227 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1231 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1233 switch (wiz->type) {
1235 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1236 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1243 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
1244 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
1256 struct wiz *wiz = dev_get_drvdata(dev);
1261 if (wiz->gpio_typec_dir) {
1262 if (wiz->typec_dir_delay)
1263 msleep_interruptible(wiz->typec_dir_delay);
1265 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1266 regmap_field_write(wiz->typec_ln10_swap, 1);
1268 regmap_field_write(wiz->typec_ln10_swap, 0);
1274 u32 num_lanes = wiz->num_lanes;
1278 if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
1279 switch (wiz->master_lane_num[i]) {
1281 regmap_field_write(wiz->typec_ln10_swap, 1);
1284 regmap_field_write(wiz->typec_ln23_swap, 1);
1295 ret = regmap_field_write(wiz->phy_reset_n, true);
1299 ret = wiz_phy_fullrt_div(wiz, id - 1);
1303 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1304 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1306 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1382 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1385 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1388 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1391 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1394 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data,
1397 .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data,
1403 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1436 wiz->master_lane_num[i] = reg;
1437 wiz->lane_phy_type[i] = phy_type;
1455 struct wiz *wiz;
1460 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1461 if (!wiz)
1470 wiz->data = data;
1471 wiz->type = data->type;
1498 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
1499 if (IS_ERR(wiz->scm_regmap)) {
1500 if (wiz->type == J7200_WIZ_10G) {
1506 wiz->scm_regmap = NULL;
1521 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1523 if (IS_ERR(wiz->gpio_typec_dir)) {
1524 ret = PTR_ERR(wiz->gpio_typec_dir);
1531 if (wiz->gpio_typec_dir) {
1533 &wiz->typec_dir_delay);
1541 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1543 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1544 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1551 ret = wiz_get_lane_phy_types(dev, wiz);
1555 wiz->dev = dev;
1556 wiz->regmap = regmap;
1557 wiz->num_lanes = num_lanes;
1558 wiz->clk_mux_sel = data->clk_mux_sel;
1559 wiz->clk_div_sel = clk_div_sel;
1560 wiz->clk_div_sel_num = data->clk_div_sel_num;
1562 platform_set_drvdata(pdev, wiz);
1564 ret = wiz_regfield_init(wiz);
1571 if (wiz->scm_regmap)
1572 regmap_field_write(wiz->sup_legacy_clk_override, 1);
1574 phy_reset_dev = &wiz->wiz_phy_reset_dev;
1595 ret = wiz_clock_init(wiz, node);
1601 for (i = 0; i < wiz->num_lanes; i++) {
1602 regmap_field_read(wiz->p_enable[i], &val);
1610 ret = wiz_init(wiz);
1623 wiz->serdes_pdev = serdes_pdev;
1629 wiz_clock_cleanup(wiz, node);
1646 struct wiz *wiz;
1648 wiz = dev_get_drvdata(dev);
1649 serdes_pdev = wiz->serdes_pdev;
1652 wiz_clock_cleanup(wiz, node);
1661 .name = "wiz",