Lines Matching defs:WIZ_MAX_LANES
47 #define WIZ_MAX_LANES 4
131 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
140 static const struct reg_field p_align[WIZ_MAX_LANES] = {
147 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
154 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
161 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
168 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
175 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
182 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
188 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
195 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
363 struct regmap_field *p_enable[WIZ_MAX_LANES];
364 struct regmap_field *p_align[WIZ_MAX_LANES];
365 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
366 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
367 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
368 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
369 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
370 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
371 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
372 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
390 u32 lane_phy_type[WIZ_MAX_LANES];
391 u32 master_lane_num[WIZ_MAX_LANES];
1515 if (num_lanes > WIZ_MAX_LANES) {