Lines Matching refs:value
468 u32 value;
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
501 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
502 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
504 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
505 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
509 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
510 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
512 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
513 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
517 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
523 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
527 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
532 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
536 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
538 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
542 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
543 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
544 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
546 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
547 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
548 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
553 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
554 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
565 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
566 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
567 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
572 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
573 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
584 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
585 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
586 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
591 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
592 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
603 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
604 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
612 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
624 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
625 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
630 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
631 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
642 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
643 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
644 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
648 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
649 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
650 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
652 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
653 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
654 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
656 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
657 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
658 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
668 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
669 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
670 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
685 u32 value;
694 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
695 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
696 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
708 u32 value;
732 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
733 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
735 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
737 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
739 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
740 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
742 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
744 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
746 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
747 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
748 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
750 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
751 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
752 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
754 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
755 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
756 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
758 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
759 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
763 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
766 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
769 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<
772 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN;
773 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
775 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
776 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
782 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
785 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<
788 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
790 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
791 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
792 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
794 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
795 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
797 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
801 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
802 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
803 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
805 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
806 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
807 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
812 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
813 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
824 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
825 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
826 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
831 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
832 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
843 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
844 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
850 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
851 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
862 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
863 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
865 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
870 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
871 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
882 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
883 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
884 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
889 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
890 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
901 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
902 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
903 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
907 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
908 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
909 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
911 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
912 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
913 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
915 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
916 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
917 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
927 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
928 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
929 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
944 u32 value;
953 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
954 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
955 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
963 u32 value;
965 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
966 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
967 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
971 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
972 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
973 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
977 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
978 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
979 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
984 u32 value;
986 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
987 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
988 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
992 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
993 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
994 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
998 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
999 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1000 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1036 u32 value;
1038 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1040 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
1045 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1049 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1053 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1064 u32 value;
1073 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1074 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1075 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1095 u32 value;
1104 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1105 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1111 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1112 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1124 u32 value;
1133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1134 value &= ~ALL_WAKE_EVENTS;
1135 value |= SS_PORT_WAKEUP_EVENT(port);
1136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1140 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1141 value &= ~ALL_WAKE_EVENTS;
1142 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1143 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1155 u32 value;
1164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1165 value &= ~ALL_WAKE_EVENTS;
1166 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1167 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1171 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1172 value &= ~ALL_WAKE_EVENTS;
1173 value |= SS_PORT_WAKEUP_EVENT(port);
1174 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1185 u32 value;
1190 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1191 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1201 u32 value;
1205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1206 value &= ~ALL_WAKE_EVENTS;
1207 value |= USB2_PORT_WAKEUP_EVENT(index);
1208 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1212 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1213 value &= ~ALL_WAKE_EVENTS;
1214 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
1215 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1226 u32 value;
1230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1231 value &= ~ALL_WAKE_EVENTS;
1232 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
1233 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1237 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1238 value &= ~ALL_WAKE_EVENTS;
1239 value |= USB2_PORT_WAKEUP_EVENT(index);
1240 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1251 u32 value;
1253 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1254 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
1255 (value & USB2_PORT_WAKEUP_EVENT(index)))
1265 u32 value;
1269 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1270 value &= ~ALL_WAKE_EVENTS;
1271 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
1272 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1276 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1277 value &= ~ALL_WAKE_EVENTS;
1278 value |= USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1290 u32 value;
1294 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1295 value &= ~ALL_WAKE_EVENTS;
1296 value &= ~USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
1297 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1301 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1302 value &= ~ALL_WAKE_EVENTS;
1303 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1315 u32 value;
1317 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1318 if ((value & USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
1319 (value & USB2_HSIC_PORT_WAKEUP_EVENT(index)))
1327 u32 value; \
1328 WARN(regmap_read(_priv->regmap, _offset, &value), "read %s failed\n", #_offset);\
1329 value; \
1341 u32 value, tctrl, pctrl, rpd_ctrl;
1349 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1350 tctrl = TCTRL_VALUE(value);
1351 pctrl = PCTRL_VALUE(value);
1353 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));
1354 rpd_ctrl = RPD_CTRL_VALUE(value);
1357 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1358 value &= ~UTMIP_MASTER_ENABLE(port);
1359 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1362 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
1363 value |= UTMIP_PWR(port);
1364 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);
1367 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
1368 value &= ~UTMIP_LINE_DEB_CNT(~0);
1369 value |= UTMIP_LINE_DEB_CNT(0x1);
1370 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);
1373 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port));
1374 value &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) |
1376 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_FAKE(port));
1379 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1380 value &= ~UTMIP_LINE_WAKEUP_EN(port);
1381 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1384 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1385 value &= ~UTMIP_WAKE_VAL(port, ~0);
1386 value |= UTMIP_WAKE_VAL_NONE(port);
1387 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1390 value = padctl_pmc_readl(priv, PMC_USB_AO);
1391 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1392 padctl_pmc_writel(priv, value, PMC_USB_AO);
1395 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1396 value &= ~SPEED(port, ~0);
1400 value |= UTMI_HS(port);
1404 value |= UTMI_FS(port);
1408 value |= UTMI_LS(port);
1412 value |= UTMI_RST(port);
1416 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1419 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1420 value |= UTMIP_LINEVAL_WALK_EN(port);
1421 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1427 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1428 value |= UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) | UTMIP_CAP_CFG(port);
1429 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1432 value = padctl_pmc_readl(priv, PMC_UTMIP_TERM_PAD_CFG);
1433 value &= ~(TCTRL_VAL(~0) | PCTRL_VAL(~0));
1434 value |= (TCTRL_VAL(tctrl) | PCTRL_VAL(pctrl));
1435 padctl_pmc_writel(priv, value, PMC_UTMIP_TERM_PAD_CFG);
1437 value = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port));
1438 value &= ~RPD_CTRL_PX(~0);
1439 value |= RPD_CTRL_PX(rpd_ctrl);
1440 padctl_pmc_writel(priv, value, PMC_UTMIP_PAD_CFGX(port));
1447 value = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port));
1448 value = UTMIP_USBOP_RPD_A | UTMIP_USBOP_RPD_B | UTMIP_USBOP_RPD_C | UTMIP_USBOP_RPD_D;
1449 value |= UTMIP_USBON_RPD_A | UTMIP_USBON_RPD_B | UTMIP_USBON_RPD_C | UTMIP_USBON_RPD_D;
1455 value |= UTMIP_HIGHZ_A;
1456 value |= UTMIP_AP_A;
1457 value |= UTMIP_AN_B | UTMIP_AN_C | UTMIP_AN_D;
1462 value |= UTMIP_HIGHZ_A;
1463 value |= UTMIP_AN_A;
1464 value |= UTMIP_AP_B | UTMIP_AP_C | UTMIP_AP_D;
1468 value |= UTMIP_HIGHZ_A | UTMIP_HIGHZ_B | UTMIP_HIGHZ_C | UTMIP_HIGHZ_D;
1472 padctl_pmc_writel(priv, value, PMC_UTMIP_SLEEPWALK_PX(port));
1475 value = padctl_pmc_readl(priv, PMC_USB_AO);
1476 value &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1477 padctl_pmc_writel(priv, value, PMC_USB_AO);
1482 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1483 value |= UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | UTMIP_TCTRL_USE_PMC(port);
1484 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1486 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1487 value |= UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port);
1488 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1491 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1492 value &= ~UTMIP_WAKE_VAL(port, ~0);
1493 value |= UTMIP_WAKE_VAL_ANY(port);
1494 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1497 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1498 value |= UTMIP_MASTER_ENABLE(port);
1499 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1501 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1502 value |= UTMIP_LINE_WAKEUP_EN(port);
1503 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1513 u32 value;
1519 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1520 value &= ~UTMIP_MASTER_ENABLE(port);
1521 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1523 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1524 value &= ~UTMIP_LINE_WAKEUP_EN(port);
1525 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1528 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1529 value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |
1531 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1533 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1534 value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));
1535 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1538 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1539 value &= ~UTMIP_WAKE_VAL(port, ~0);
1540 value |= UTMIP_WAKE_VAL_NONE(port);
1541 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1544 value = padctl_pmc_readl(priv, PMC_USB_AO);
1545 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1546 padctl_pmc_writel(priv, value, PMC_USB_AO);
1549 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1550 value |= UTMIP_CLR_WAKE_ALARM(port);
1551 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1561 u32 value;
1567 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1568 value &= ~UHSIC_MASTER_ENABLE;
1569 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1572 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
1573 value |= UHSIC_PWR;
1574 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);
1577 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
1578 value &= ~UHSIC_LINE_DEB_CNT(~0);
1579 value |= UHSIC_LINE_DEB_CNT(0x1);
1580 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);
1583 value = padctl_pmc_readl(priv, PMC_UHSIC_FAKE);
1584 value &= ~(UHSIC_FAKE_STROBE_VAL | UHSIC_FAKE_DATA_VAL |
1586 padctl_pmc_writel(priv, value, PMC_UHSIC_FAKE);
1589 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1590 value &= ~UHSIC_LINE_WAKEUP_EN;
1591 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1594 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1595 value &= ~UHSIC_WAKE_VAL(~0);
1596 value |= UHSIC_WAKE_VAL_NONE;
1597 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1600 value = padctl_pmc_readl(priv, PMC_USB_AO);
1601 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;
1602 padctl_pmc_writel(priv, value, PMC_USB_AO);
1605 value = padctl_pmc_readl(priv, PMC_UHSIC_SAVED_STATE);
1606 value &= ~UHSIC_MODE(~0);
1607 value |= UHSIC_HS;
1608 padctl_pmc_writel(priv, value, PMC_UHSIC_SAVED_STATE);
1611 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_CFG);
1612 value |= UHSIC_WAKE_WALK_EN | UHSIC_LINEVAL_WALK_EN;
1613 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_CFG);
1619 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1620 value |= UHSIC_CLR_WALK_PTR | UHSIC_CLR_WAKE_ALARM;
1621 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1628 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_P0);
1629 value = UHSIC_DATA0_RPD_A | UHSIC_DATA0_RPU_B | UHSIC_DATA0_RPU_C | UHSIC_DATA0_RPU_D |
1631 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_P0);
1634 value = padctl_pmc_readl(priv, PMC_USB_AO);
1635 value &= ~(STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD);
1636 padctl_pmc_writel(priv, value, PMC_USB_AO);
1641 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1642 value &= ~UHSIC_WAKE_VAL(~0);
1643 value |= UHSIC_WAKE_VAL_SD10;
1644 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1647 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1648 value |= UHSIC_MASTER_ENABLE;
1649 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1651 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1652 value |= UHSIC_LINE_WAKEUP_EN;
1653 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1662 u32 value;
1668 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1669 value &= ~UHSIC_MASTER_ENABLE;
1670 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1672 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1673 value &= ~UHSIC_LINE_WAKEUP_EN;
1674 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1677 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1678 value &= ~UHSIC_WAKE_VAL(~0);
1679 value |= UHSIC_WAKE_VAL_NONE;
1680 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1683 value = padctl_pmc_readl(priv, PMC_USB_AO);
1684 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;
1685 padctl_pmc_writel(priv, value, PMC_USB_AO);
1688 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1689 value |= UHSIC_CLR_WAKE_ALARM;
1690 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1700 u32 value, offset;
1713 value = padctl_readl(padctl, offset);
1715 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<
1721 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<
1727 padctl_writel(padctl, value, offset);
1805 u32 value;
1821 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1822 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
1824 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<
1826 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1858 u32 value;
1862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1865 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1866 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1868 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
1871 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1874 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1882 u32 value;
1886 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1889 if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) {
1890 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1891 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1894 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1897 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1899 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED <<
1902 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1904 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
1908 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1961 u32 value;
1975 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1976 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
1978 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
1980 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1982 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1983 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1985 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1989 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1990 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1992 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1996 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1997 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1999 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2002 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2003 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
2007 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
2011 value |=
2015 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2017 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
2018 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
2020 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
2022 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
2024 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
2026 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
2027 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
2029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
2030 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
2035 value |= (priv->fuse.hs_curr_level[index] +
2038 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
2040 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2041 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
2048 value |= (priv->fuse.hs_term_range_adj <<
2052 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2054 value = padctl_readl(padctl,
2056 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
2059 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
2061 value |=
2064 padctl_writel(padctl, value,
2077 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2078 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
2082 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
2086 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2088 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2089 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
2090 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2094 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2095 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
2096 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2118 u32 value;
2130 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2131 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
2133 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2138 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
2140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2145 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
2147 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2149 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2150 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
2152 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2161 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2162 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
2163 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2298 u32 value;
2300 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
2301 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<
2303 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<
2305 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
2322 u32 value;
2332 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2333 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<
2335 value |= (hsic->tx_rtune_p <<
2337 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2339 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2340 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
2344 value |= (hsic->rx_strobe_trim <<
2348 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2350 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2351 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
2363 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
2366 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2372 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2373 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<
2377 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<
2381 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2385 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2386 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;
2387 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2406 u32 value;
2408 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2409 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
2418 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2499 u32 value;
2501 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2502 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
2503 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2504 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
2505 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
2506 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
2507 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
2508 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
2509 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
2510 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
2511 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
2512 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2518 u32 value;
2520 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2521 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
2522 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2523 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
2524 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
2525 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
2526 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
2527 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
2528 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
2529 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
2530 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
2531 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2584 u32 value;
2593 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2596 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2598 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2600 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2601 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
2602 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2605 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
2607 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
2609 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2612 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
2614 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
2616 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2621 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2622 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
2624 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
2626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2631 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2632 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2633 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2637 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2638 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2639 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2643 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2644 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2645 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2657 u32 value;
2666 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2667 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2668 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2672 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2673 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2674 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2678 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2679 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2680 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
3090 u32 value;
3095 value = padctl_readl(padctl,
3098 if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||
3099 (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {
3112 u32 value;
3115 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
3121 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
3126 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
3129 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
3134 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &