Lines Matching defs:port
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",
455 lane->pad->soc->lanes[lane->index].name, map->port);
456 return map->port;
1062 int port = tegra210_usb3_lane_map(lane);
1066 if (port < 0) {
1067 dev_err(dev, "invalid usb3 port number\n");
1074 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1093 int port = tegra210_usb3_lane_map(lane);
1097 if (port < 0) {
1098 dev_err(dev, "invalid usb3 port number\n");
1105 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1111 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1122 int port = tegra210_usb3_lane_map(lane);
1126 if (port < 0) {
1127 dev_err(dev, "invalid usb3 port number\n");
1135 value |= SS_PORT_WAKEUP_EVENT(port);
1142 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1153 int port = tegra210_usb3_lane_map(lane);
1157 if (port < 0) {
1158 dev_err(dev, "invalid usb3 port number\n");
1166 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1173 value |= SS_PORT_WAKEUP_EVENT(port);
1340 unsigned int port = lane->index;
1353 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));
1357 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1358 value &= ~UTMIP_MASTER_ENABLE(port);
1359 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1363 value |= UTMIP_PWR(port);
1373 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port));
1374 value &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) |
1375 UTMIP_FAKE_USBOP_EN(port) | UTMIP_FAKE_USBON_EN(port));
1376 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_FAKE(port));
1380 value &= ~UTMIP_LINE_WAKEUP_EN(port);
1384 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1385 value &= ~UTMIP_WAKE_VAL(port, ~0);
1386 value |= UTMIP_WAKE_VAL_NONE(port);
1387 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1391 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1395 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1396 value &= ~SPEED(port, ~0);
1400 value |= UTMI_HS(port);
1404 value |= UTMI_FS(port);
1408 value |= UTMI_LS(port);
1412 value |= UTMI_RST(port);
1416 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1419 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1420 value |= UTMIP_LINEVAL_WALK_EN(port);
1421 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1428 value |= UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) | UTMIP_CAP_CFG(port);
1437 value = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port));
1440 padctl_pmc_writel(priv, value, PMC_UTMIP_PAD_CFGX(port));
1447 value = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port));
1472 padctl_pmc_writel(priv, value, PMC_UTMIP_SLEEPWALK_PX(port));
1476 value &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1482 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1483 value |= UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | UTMIP_TCTRL_USE_PMC(port);
1484 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1487 value |= UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port);
1491 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1492 value &= ~UTMIP_WAKE_VAL(port, ~0);
1493 value |= UTMIP_WAKE_VAL_ANY(port);
1494 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1497 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1498 value |= UTMIP_MASTER_ENABLE(port);
1499 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1502 value |= UTMIP_LINE_WAKEUP_EN(port);
1512 unsigned int port = lane->index;
1519 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1520 value &= ~UTMIP_MASTER_ENABLE(port);
1521 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1524 value &= ~UTMIP_LINE_WAKEUP_EN(port);
1528 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1529 value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |
1530 UTMIP_TCTRL_USE_PMC(port));
1531 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1534 value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));
1538 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1539 value &= ~UTMIP_WAKE_VAL(port, ~0);
1540 value |= UTMIP_WAKE_VAL_NONE(port);
1541 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1543 /* power down the line state detectors of the port */
1545 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1550 value |= UTMIP_CLR_WAKE_ALARM(port);
1599 /* power down the line state detectors of the port */
1617 * as well as capture the configuration of the USB2.0 port.
1633 /* power up the line state detectors of the port */
1682 /* power down the line state detectors of the port */
1698 struct tegra_xusb_port *port;
1702 port = tegra_xusb_find_port(padctl, "usb3", index);
1703 if (!port)
1706 lane = port->lane;
1803 struct tegra_xusb_usb2_port *port;
1807 port = tegra_xusb_find_usb2_port(padctl, index);
1808 if (!port) {
1809 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
1813 if (port->supply && port->mode == USB_DR_MODE_HOST) {
1814 err = regulator_enable(port->supply);
1837 struct tegra_xusb_usb2_port *port;
1840 port = tegra_xusb_find_usb2_port(padctl, lane->index);
1841 if (!port) {
1842 dev_err(&phy->dev, "no port found for USB2 lane %u\n", lane->index);
1846 if (port->supply && port->mode == USB_DR_MODE_HOST) {
1847 err = regulator_disable(port->supply);
1918 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
1924 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
1930 err = regulator_enable(port->supply);
1935 * When port is peripheral only or role transitions to
1939 if (regulator_is_enabled(port->supply))
1940 regulator_disable(port->supply);
1959 struct tegra_xusb_usb2_port *port;
1964 port = tegra_xusb_find_usb2_port(padctl, index);
1965 if (!port) {
1966 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
1974 if (port->usb3_port_fake != -1) {
1977 port->usb3_port_fake);
1979 port->usb3_port_fake, index);
1984 port->usb3_port_fake);
1991 port->usb3_port_fake);
1998 port->usb3_port_fake);
2019 if (port->mode == USB_DR_MODE_UNKNOWN)
2021 else if (port->mode == USB_DR_MODE_PERIPHERAL)
2023 else if (port->mode == USB_DR_MODE_HOST)
2025 else if (port->mode == USB_DR_MODE_OTG)
2058 if (port->mode == USB_DR_MODE_HOST)
2117 struct tegra_xusb_usb2_port *port;
2120 port = tegra_xusb_find_usb2_port(padctl, lane->index);
2121 if (!port) {
2122 dev_err(&phy->dev, "no port found for USB2 lane %u\n",
2129 if (port->usb3_port_fake != -1) {
2132 port->usb3_port_fake);
2139 port->usb3_port_fake);
2146 port->usb3_port_fake);
2150 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
2565 int port;
2570 port = tegra210_usb3_lane_map(lane);
2571 if (port < 0)
2574 return tegra_xusb_find_usb3_port(lane->pad->padctl, port);
2587 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
2601 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
2660 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
3019 static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)
3024 static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)
3029 tegra210_usb2_port_map(struct tegra_xusb_port *port)
3031 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
3042 static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)
3047 static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)
3052 tegra210_hsic_port_map(struct tegra_xusb_port *port)
3054 return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
3064 static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
3069 static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
3074 tegra210_usb3_port_map(struct tegra_xusb_port *port)
3076 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");