Lines Matching defs:pcie
438 { 0, "pcie", 6 },
439 { 1, "pcie", 5 },
440 { 2, "pcie", 0 },
441 { 2, "pcie", 3 },
442 { 3, "pcie", 4 },
466 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
472 if (pcie->enable)
475 err = clk_prepare_enable(pcie->pll);
482 err = reset_control_deassert(pcie->rst);
665 pcie->enable = true;
667 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
676 reset_control_assert(pcie->rst);
678 clk_disable_unprepare(pcie->pll);
684 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
688 if (WARN_ON(!pcie->enable))
691 pcie->enable = false;
693 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
699 clk_disable_unprepare(pcie->pll);
1005 if (padctl->pcie)
1029 if (padctl->pcie)
1708 if (lane->pad == padctl->pcie)
2546 "pcie-x1",
2549 "pcie-x4",
2553 TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
2554 TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),
2555 TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),
2556 TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),
2557 TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),
2558 TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),
2559 TEGRA210_UPHY_LANE("pcie-6", 0x028, 24, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(6)),
2688 struct tegra_xusb_pcie_lane *pcie;
2691 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
2692 if (!pcie)
2695 INIT_LIST_HEAD(&pcie->base.list);
2696 pcie->base.soc = &pad->soc->lanes[index];
2697 pcie->base.index = index;
2698 pcie->base.pad = pad;
2699 pcie->base.np = np;
2701 err = tegra_xusb_lane_parse_dt(&pcie->base, np);
2703 kfree(pcie);
2707 return &pcie->base;
2712 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
2714 kfree(pcie);
2785 struct tegra_xusb_pcie_pad *pcie;
2789 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
2790 if (!pcie)
2793 pad = &pcie->base;
2799 kfree(pcie);
2803 pcie->pll = devm_clk_get(&pad->dev, "pll");
2804 if (IS_ERR(pcie->pll)) {
2805 err = PTR_ERR(pcie->pll);
2810 pcie->rst = devm_reset_control_get(&pad->dev, "phy");
2811 if (IS_ERR(pcie->rst)) {
2812 err = PTR_ERR(pcie->rst);
2833 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
2835 kfree(pcie);
2844 .name = "pcie",
2851 TEGRA210_UPHY_LANE("sata-0", 0x028, 30, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2),