Lines Matching refs:padctl
274 /* padctl context */
289 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
291 return container_of(padctl, struct tegra186_xusb_padctl, base);
331 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
332 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
336 mutex_lock(&padctl->lock);
428 if (padctl->soc->supports_lp_cfg_en)
437 if (padctl->soc->supports_lp_cfg_en)
472 mutex_unlock(&padctl->lock);
479 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
480 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
484 mutex_lock(&padctl->lock);
503 if (padctl->soc->supports_lp_cfg_en) {
520 mutex_unlock(&padctl->lock);
527 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
531 mutex_lock(&padctl->lock);
533 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
536 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
540 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
543 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
545 mutex_unlock(&padctl->lock);
552 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
556 mutex_lock(&padctl->lock);
558 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
561 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
565 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
568 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
570 mutex_unlock(&padctl->lock);
577 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
581 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
599 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
601 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
602 struct device *dev = padctl->dev;
606 mutex_lock(&padctl->lock);
609 mutex_unlock(&padctl->lock);
617 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
622 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
624 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
628 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
636 if (padctl->soc->poll_trk_completed) {
637 err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
646 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
648 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
653 if (padctl->soc->trk_hw_mode) {
654 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
657 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
662 mutex_unlock(&padctl->lock);
665 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
667 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
670 mutex_lock(&padctl->lock);
673 mutex_unlock(&padctl->lock);
678 mutex_unlock(&padctl->lock);
682 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
684 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
686 if (padctl->soc->trk_hw_mode) {
687 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
689 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
693 mutex_unlock(&padctl->lock);
699 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
701 struct device *dev = padctl->dev;
708 port = tegra_xusb_find_usb2_port(padctl, index);
716 tegra186_utmi_bias_pad_power_on(padctl);
720 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
722 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
724 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
726 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
732 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
739 dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
741 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
743 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
745 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
747 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
751 tegra186_utmi_bias_pad_power_off(padctl);
754 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
759 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
761 value = padctl_readl(padctl, USB2_VBUS_ID);
771 padctl_writel(padctl, value, USB2_VBUS_ID);
776 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
781 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
783 value = padctl_readl(padctl, USB2_VBUS_ID);
788 padctl_writel(padctl, value, USB2_VBUS_ID);
791 value = padctl_readl(padctl, USB2_VBUS_ID);
801 padctl_writel(padctl, value, USB2_VBUS_ID);
810 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
811 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
815 mutex_lock(&padctl->lock);
821 tegra186_xusb_padctl_id_override(padctl, true);
825 tegra186_xusb_padctl_vbus_override(padctl, true);
835 tegra186_xusb_padctl_id_override(padctl, false);
836 tegra186_xusb_padctl_vbus_override(padctl, false);
840 mutex_unlock(&padctl->lock);
849 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
850 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
853 struct device *dev = padctl->dev;
856 port = tegra_xusb_find_usb2_port(padctl, index);
862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
865 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
867 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
879 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
881 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
902 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
904 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
909 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
926 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
929 struct device *dev = padctl->dev;
932 port = tegra_xusb_find_usb2_port(padctl, index);
953 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
956 struct device *dev = padctl->dev;
959 port = tegra_xusb_find_usb2_port(padctl, index);
987 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
991 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1004 err = tegra_xusb_pad_init(pad, padctl, np);
1059 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1107 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1111 mutex_lock(&padctl->lock);
1113 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1115 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1119 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1121 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1125 mutex_unlock(&padctl->lock);
1132 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1136 mutex_lock(&padctl->lock);
1138 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1146 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1148 mutex_unlock(&padctl->lock);
1155 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1159 mutex_lock(&padctl->lock);
1161 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1164 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1168 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1171 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1173 mutex_unlock(&padctl->lock);
1180 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1184 mutex_lock(&padctl->lock);
1186 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1189 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1193 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1196 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1198 mutex_unlock(&padctl->lock);
1205 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1209 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1238 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1251 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1255 struct device *dev = padctl->dev;
1258 port = tegra_xusb_find_usb3_port(padctl, index);
1264 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1271 mutex_lock(&padctl->lock);
1273 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1285 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1287 if (padctl->soc->supports_gen2 && port->disable_gen2) {
1288 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1293 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1296 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1298 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1302 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1308 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1310 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1312 mutex_unlock(&padctl->lock);
1320 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1323 struct device *dev = padctl->dev;
1326 port = tegra_xusb_find_usb3_port(padctl, index);
1332 mutex_lock(&padctl->lock);
1334 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1336 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1340 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1342 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1346 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1348 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1350 mutex_unlock(&padctl->lock);
1374 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1390 err = tegra_xusb_pad_init(pad, padctl, np);
1427 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1429 struct device *dev = padctl->base.dev;
1434 count = padctl->base.soc->ports.usb2.count;
1451 padctl->calib.hs_curr_level = level;
1453 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1455 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1466 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1499 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1501 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1503 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1504 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1505 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1506 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1509 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1511 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1513 padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1514 padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1515 padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1516 padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1519 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1521 tegra186_xusb_padctl_save(padctl);
1526 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1528 tegra186_xusb_padctl_restore(padctl);
1533 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)