Lines Matching refs:port
279 /* Check if a phy port is still active or clk48 in use */
293 * Check if a phy port or clk48 prepare has configured the pll
582 int port = 0;
584 for (port = 0; port < usbphyc->nphys; port++) {
585 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
586 usbphyc_phy = usbphyc->phys[port];
597 dev_err(dev, "invalid number of cells for phy port%d\n",
602 /* Configure the UTMI switch for PHY port#2 */
624 int ret, port = 0;
703 port, ret);
722 usbphyc->phys[port] = usbphyc_phy;
726 usbphyc->phys[port]->phy = phy;
727 usbphyc->phys[port]->usbphyc = usbphyc;
728 usbphyc->phys[port]->index = index;
729 usbphyc->phys[port]->active = false;
731 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
732 if (IS_ERR(usbphyc->phys[port]->vbus)) {
733 ret = PTR_ERR(usbphyc->phys[port]->vbus);
736 usbphyc->phys[port]->vbus = NULL;
742 port++;
776 int port;
779 for (port = 0; port < usbphyc->nphys; port++)
780 if (usbphyc->phys[port]->active)
781 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
792 int port;
797 for (port = 0; port < usbphyc->nphys; port++) {
798 usbphyc_phy = usbphyc->phys[port];
799 writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));