Lines Matching refs:ret
415 int ret;
420 ret = clk_prepare_enable(phy_drd->clk);
421 if (ret)
422 return ret;
477 int ret;
482 ret = clk_prepare_enable(phy_drd->clk);
483 if (ret)
484 return ret;
511 int ret;
526 ret = regulator_enable(phy_drd->vbus_boost);
527 if (ret) {
535 ret = regulator_enable(phy_drd->vbus);
536 if (ret) {
559 return ret;
618 int ret;
623 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
625 if (ret)
626 return ret;
631 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
633 if (ret)
634 return ret;
636 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
639 return ret;
650 int ret = 0;
661 ret = crport_ctrl_write(phy_drd,
664 if (ret) {
667 return ret;
675 ret = crport_ctrl_write(phy_drd,
678 if (ret) {
681 return ret;
707 ret = crport_ctrl_write(phy_drd,
710 if (ret)
714 return ret;
812 int ret;
814 ret = clk_prepare_enable(phy_drd->clk);
815 if (ret)
816 return ret;
832 int ret;
834 ret = clk_prepare_enable(phy_drd->clk);
835 if (ret)
836 return ret;
873 int ret;
888 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
889 if (ret) {
892 return ret;
1011 int i, ret;
1031 ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
1032 if (ret) {
1034 return ret;
1066 ret = PTR_ERR(phy_drd->vbus);
1067 if (ret == -EPROBE_DEFER)
1068 return ret;
1076 ret = PTR_ERR(phy_drd->vbus_boost);
1077 if (ret == -EPROBE_DEFER)
1078 return ret;