Lines Matching defs:phy_drd
191 void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
312 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
315 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
325 switch (phy_drd->extrefclk) {
343 dev_dbg(phy_drd->dev, "unsupported ref clk\n");
358 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
361 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
369 reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
374 static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
378 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
382 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
384 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
386 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
389 static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
393 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
397 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
399 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
403 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
406 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
408 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
410 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
418 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
420 ret = clk_prepare_enable(phy_drd->clk);
425 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
426 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
434 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
436 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
439 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
442 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
444 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
447 inst->phy_cfg->phy_init(phy_drd);
463 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
468 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
470 clk_disable_unprepare(phy_drd->clk);
480 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
482 ret = clk_prepare_enable(phy_drd->clk);
489 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
492 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
496 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
499 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
502 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
504 clk_disable_unprepare(phy_drd->clk);
513 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
515 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
517 clk_prepare_enable(phy_drd->ref_clk);
518 if (!phy_drd->drv_data->has_common_clk_gate) {
519 clk_prepare_enable(phy_drd->pipeclk);
520 clk_prepare_enable(phy_drd->utmiclk);
521 clk_prepare_enable(phy_drd->itpclk);
525 if (phy_drd->vbus_boost) {
526 ret = regulator_enable(phy_drd->vbus_boost);
528 dev_err(phy_drd->dev,
534 if (phy_drd->vbus) {
535 ret = regulator_enable(phy_drd->vbus);
537 dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
548 if (phy_drd->vbus_boost)
549 regulator_disable(phy_drd->vbus_boost);
552 clk_disable_unprepare(phy_drd->ref_clk);
553 if (!phy_drd->drv_data->has_common_clk_gate) {
554 clk_disable_unprepare(phy_drd->itpclk);
555 clk_disable_unprepare(phy_drd->utmiclk);
556 clk_disable_unprepare(phy_drd->pipeclk);
565 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
567 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
573 if (phy_drd->vbus)
574 regulator_disable(phy_drd->vbus);
575 if (phy_drd->vbus_boost)
576 regulator_disable(phy_drd->vbus_boost);
578 clk_disable_unprepare(phy_drd->ref_clk);
579 if (!phy_drd->drv_data->has_common_clk_gate) {
580 clk_disable_unprepare(phy_drd->itpclk);
581 clk_disable_unprepare(phy_drd->pipeclk);
582 clk_disable_unprepare(phy_drd->utmiclk);
588 static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
594 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
596 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
599 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val);
603 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
605 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
608 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val);
615 static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
622 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
623 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
630 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
631 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
636 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
647 static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
661 ret = crport_ctrl_write(phy_drd,
665 dev_err(phy_drd->dev,
675 ret = crport_ctrl_write(phy_drd,
679 dev_err(phy_drd->dev,
693 switch (phy_drd->extrefclk) {
707 ret = crport_ctrl_write(phy_drd,
711 dev_err(phy_drd->dev,
720 struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
725 return phy_drd->phys[args->args[0]].phy;
731 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
734 return exynos5420_usbdrd_phy_calibrate(phy_drd);
747 static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
749 void __iomem *regs_base = phy_drd->reg_phy;
811 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
814 ret = clk_prepare_enable(phy_drd->clk);
819 inst->phy_cfg->phy_init(phy_drd);
821 clk_disable_unprepare(phy_drd->clk);
829 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
830 void __iomem *regs_base = phy_drd->reg_phy;
834 ret = clk_prepare_enable(phy_drd->clk);
857 clk_disable_unprepare(phy_drd->clk);
870 static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
875 phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
876 if (IS_ERR(phy_drd->clk)) {
877 dev_err(phy_drd->dev, "Failed to get phy clock\n");
878 return PTR_ERR(phy_drd->clk);
881 phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
882 if (IS_ERR(phy_drd->ref_clk)) {
883 dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
884 return PTR_ERR(phy_drd->ref_clk);
886 ref_rate = clk_get_rate(phy_drd->ref_clk);
888 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
890 dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
895 if (!phy_drd->drv_data->has_common_clk_gate) {
896 phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
897 if (IS_ERR(phy_drd->pipeclk)) {
898 dev_info(phy_drd->dev,
900 phy_drd->pipeclk = NULL;
903 phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
904 if (IS_ERR(phy_drd->utmiclk)) {
905 dev_info(phy_drd->dev,
907 phy_drd->utmiclk = NULL;
910 phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
911 if (IS_ERR(phy_drd->itpclk)) {
912 dev_info(phy_drd->dev,
914 phy_drd->itpclk = NULL;
1006 struct exynos5_usbdrd_phy *phy_drd;
1014 phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
1015 if (!phy_drd)
1018 dev_set_drvdata(dev, phy_drd);
1019 phy_drd->dev = dev;
1021 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0);
1022 if (IS_ERR(phy_drd->reg_phy))
1023 return PTR_ERR(phy_drd->reg_phy);
1029 phy_drd->drv_data = drv_data;
1031 ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
1055 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
1059 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
1064 phy_drd->vbus = devm_regulator_get(dev, "vbus");
1065 if (IS_ERR(phy_drd->vbus)) {
1066 ret = PTR_ERR(phy_drd->vbus);
1071 phy_drd->vbus = NULL;
1074 phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
1075 if (IS_ERR(phy_drd->vbus_boost)) {
1076 ret = PTR_ERR(phy_drd->vbus_boost);
1081 phy_drd->vbus_boost = NULL;
1094 phy_drd->phys[i].phy = phy;
1095 phy_drd->phys[i].index = i;
1096 phy_drd->phys[i].reg_pmu = reg_pmu;
1097 phy_drd->phys[i].pmu_offset = pmu_offset;
1098 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
1099 phy_set_drvdata(phy, &phy_drd->phys[i]);
1105 dev_err(phy_drd->dev, "Failed to register phy provider\n");