Lines Matching defs:rk_phy
88 struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
91 return rk_phy->phys[0].phy;
96 return rk_phy->phys[args->args[0]].phy;
100 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
103 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
111 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
116 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
125 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
128 mutex_lock(&rk_phy->pcie_mutex);
130 regmap_write(rk_phy->reg_base,
131 rk_phy->phy_data->pcie_laneoff,
136 if (--rk_phy->pwr_cnt)
139 err = reset_control_assert(rk_phy->phy_rst);
146 mutex_unlock(&rk_phy->pcie_mutex);
150 rk_phy->pwr_cnt++;
151 regmap_write(rk_phy->reg_base,
152 rk_phy->phy_data->pcie_laneoff,
156 mutex_unlock(&rk_phy->pcie_mutex);
163 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
168 mutex_lock(&rk_phy->pcie_mutex);
170 if (rk_phy->pwr_cnt++)
173 err = reset_control_deassert(rk_phy->phy_rst);
179 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
184 regmap_write(rk_phy->reg_base,
185 rk_phy->phy_data->pcie_laneoff,
199 regmap_read(rk_phy->reg_base,
200 rk_phy->phy_data->pcie_status,
215 phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
216 phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
220 regmap_read(rk_phy->reg_base,
221 rk_phy->phy_data->pcie_status,
236 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
242 regmap_read(rk_phy->reg_base,
243 rk_phy->phy_data->pcie_status,
259 mutex_unlock(&rk_phy->pcie_mutex);
263 reset_control_assert(rk_phy->phy_rst);
265 rk_phy->pwr_cnt--;
266 mutex_unlock(&rk_phy->pcie_mutex);
273 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
276 mutex_lock(&rk_phy->pcie_mutex);
278 if (rk_phy->init_cnt++)
281 err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
287 err = reset_control_assert(rk_phy->phy_rst);
294 mutex_unlock(&rk_phy->pcie_mutex);
299 clk_disable_unprepare(rk_phy->clk_pciephy_ref);
301 rk_phy->init_cnt--;
302 mutex_unlock(&rk_phy->pcie_mutex);
309 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
311 mutex_lock(&rk_phy->pcie_mutex);
313 if (--rk_phy->init_cnt)
316 clk_disable_unprepare(rk_phy->clk_pciephy_ref);
319 mutex_unlock(&rk_phy->pcie_mutex);
350 struct rockchip_pcie_phy *rk_phy;
363 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
364 if (!rk_phy)
371 rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
372 rk_phy->reg_base = grf;
374 mutex_init(&rk_phy->pcie_mutex);
376 rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
377 if (IS_ERR(rk_phy->phy_rst)) {
378 if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
381 return PTR_ERR(rk_phy->phy_rst);
384 rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
385 if (IS_ERR(rk_phy->clk_pciephy_ref)) {
387 return PTR_ERR(rk_phy->clk_pciephy_ref);
398 rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
399 if (IS_ERR(rk_phy->phys[i].phy)) {
401 return PTR_ERR(rk_phy->phys[i].phy);
403 rk_phy->phys[i].index = i;
404 phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
407 platform_set_drvdata(pdev, rk_phy);