Lines Matching refs:port_cfg
198 * @port_cfg: port register configuration, assigned by driver data.
217 const struct rockchip_usb2phy_port_cfg *port_cfg;
454 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
458 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
462 ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
466 return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
482 &rport->port_cfg->bvalid_det_clr,
488 &rport->port_cfg->bvalid_det_en,
495 &rport->port_cfg->id_det_clr,
501 &rport->port_cfg->id_det_en,
513 if (rport->port_cfg->disfall_en.offset) {
524 &rport->port_cfg->ls_det_clr, true);
529 &rport->port_cfg->ls_det_en, true);
557 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
594 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
638 &rport->port_cfg->utmi_bvalid);
901 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
905 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
906 rport->port_cfg->utmi_ls.bitstart);
908 if (rport->port_cfg->utmi_hstdet.offset) {
909 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
913 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
914 rport->port_cfg->utmi_hstdet.bitstart);
916 sh = rport->port_cfg->utmi_hstdet.bitend -
917 rport->port_cfg->utmi_hstdet.bitstart + 1;
919 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
920 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
922 state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
967 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
968 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
991 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
997 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
998 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
1018 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
1022 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
1035 if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
1039 property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
1041 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1062 if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
1063 !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
1069 if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
1070 property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
1072 } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1073 property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
1095 rport->port_cfg->disfall_en.offset)
1216 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1249 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1291 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);