Lines Matching refs:phy_cfg
238 * @phy_cfg: phy register configuration, assigned by driver data.
254 const struct rockchip_usb2phy_cfg *phy_cfg;
317 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
318 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
336 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
345 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
760 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
761 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
769 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
770 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
778 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
779 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
802 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
812 &rphy->phy_cfg->chg_det.dp_det);
830 &rphy->phy_cfg->chg_det.cp_det);
852 &rphy->phy_cfg->chg_det.dcp_det);
865 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
1089 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1216 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1249 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1372 rphy->phy_cfg = &phy_cfgs[index];
1379 if (!rphy->phy_cfg) {
1400 if (rphy->phy_cfg->phy_tuning) {
1401 ret = rphy->phy_cfg->phy_tuning(rphy);
1441 if (++index >= rphy->phy_cfg->num_ports) {
1479 if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
1483 } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {