Lines Matching refs:inno
280 int (*init)(struct inno_hdmi_phy *inno);
281 int (*power_on)(struct inno_hdmi_phy *inno,
284 void (*power_off)(struct inno_hdmi_phy *inno);
530 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
532 regmap_write(inno->regmap, reg * 4, val);
535 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
539 regmap_read(inno->regmap, reg * 4, &val);
544 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
547 regmap_update_bits(inno->regmap, reg * 4, mask, val);
550 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
551 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
554 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
557 int bus_width = phy_get_bus_width(inno->phy);
574 struct inno_hdmi_phy *inno = dev_id;
577 intr_stat1 = inno_read(inno, 0x04);
578 intr_stat2 = inno_read(inno, 0x06);
579 intr_stat3 = inno_read(inno, 0x08);
582 inno_write(inno, 0x04, intr_stat1);
584 inno_write(inno, 0x06, intr_stat2);
586 inno_write(inno, 0x08, intr_stat3);
596 struct inno_hdmi_phy *inno = dev_id;
598 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
600 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
607 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
609 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
610 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
611 inno->pixclock);
615 dev_err(inno->dev, "TMDS clock is zero!\n");
619 if (!inno->plat_data->ops->power_on)
624 cfg->version & inno->chip_version)
634 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
636 inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
638 ret = clk_prepare_enable(inno->phyclk);
642 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
644 clk_disable_unprepare(inno->phyclk);
653 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
655 if (!inno->plat_data->ops->power_off)
658 inno->plat_data->ops->power_off(inno);
660 clk_disable_unprepare(inno->phyclk);
662 inno->tmdsclock = 0;
664 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
676 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
680 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
694 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
697 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
703 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
705 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
711 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
713 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
721 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
726 nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
727 nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
728 nf |= inno_read(inno, 0xe3);
731 if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
734 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
737 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
740 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
745 inno->pixclock = vco;
747 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
774 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
776 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
780 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
783 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
786 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
791 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
794 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
800 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
801 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
805 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
809 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
817 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
820 ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
823 dev_err(inno->dev, "Pre-PLL locking failed\n");
827 inno->pixclock = rate;
828 inno->tmdsclock = tmdsclock;
844 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
847 status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
853 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
855 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
861 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
863 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
871 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
877 nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
878 nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
879 nf |= inno_read(inno, 0xa3);
882 if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
883 frac = inno_read(inno, 0xd3) |
884 (inno_read(inno, 0xd2) << 8) |
885 (inno_read(inno, 0xd1) << 16);
889 if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
892 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
893 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
896 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
901 inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
903 dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
904 __func__, inno->pixclock, vco);
906 return inno->pixclock;
931 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
933 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
937 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
940 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
943 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
947 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
951 inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
953 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
958 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
959 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
960 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
962 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
964 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
967 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
968 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
969 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
971 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
974 ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
977 dev_err(inno->dev, "Pre-PLL locking failed\n");
981 inno->pixclock = rate;
982 inno->tmdsclock = tmdsclock;
996 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
998 struct device *dev = inno->dev;
1004 parent_name = __clk_get_name(inno->refoclk);
1010 init.ops = inno->plat_data->clk_ops;
1015 inno->hw.init = &init;
1017 inno->phyclk = devm_clk_register(dev, &inno->hw);
1018 if (IS_ERR(inno->phyclk)) {
1019 ret = PTR_ERR(inno->phyclk);
1024 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
1033 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
1039 inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
1042 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
1046 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
1049 inno->chip_version = 1;
1055 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
1062 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
1064 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1070 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
1072 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
1074 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1077 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1082 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1084 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
1089 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
1091 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1093 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
1095 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
1099 ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
1102 dev_err(inno->dev, "Post-PLL locking failed\n");
1109 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
1113 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
1115 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
1116 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
1117 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
1127 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
1137 inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
1140 inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
1144 inno_write(inno, 0x05, 0);
1145 inno_write(inno, 0x07, 0);
1148 inno->chip_version = 1;
1149 cell = nvmem_cell_get(inno->dev, "cpu-version");
1163 inno->chip_version = efuse_buf[0] + 1;
1170 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1177 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1178 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1181 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1183 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1185 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
1190 inno_write(inno, 0xad, v);
1191 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1193 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1199 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1203 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1208 v = clk_get_rate(inno->sysclk) / 100000;
1209 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1211 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1212 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1213 inno_update_bits(inno, 0xc5,
1216 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1220 inno_update_bits(inno, 0xc8,
1227 inno_update_bits(inno, 0xc9 + v,
1232 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1233 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1235 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1239 ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1242 dev_err(inno->dev, "Post-PLL locking failed\n");
1249 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1252 inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1254 inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1259 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1261 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1262 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1263 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1267 inno_write(inno, 0x05, 0);
1268 inno_write(inno, 0x07, 0);
1298 struct inno_hdmi_phy *inno = data;
1300 clk_disable_unprepare(inno->refpclk);
1301 clk_disable_unprepare(inno->sysclk);
1306 struct inno_hdmi_phy *inno;
1311 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1312 if (!inno)
1315 inno->dev = &pdev->dev;
1317 inno->plat_data = of_device_get_match_data(inno->dev);
1318 if (!inno->plat_data || !inno->plat_data->ops)
1325 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1326 if (IS_ERR(inno->sysclk)) {
1327 ret = PTR_ERR(inno->sysclk);
1328 dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1332 inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1333 if (IS_ERR(inno->refpclk)) {
1334 ret = PTR_ERR(inno->refpclk);
1335 dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1339 inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1340 if (IS_ERR(inno->refoclk)) {
1341 ret = PTR_ERR(inno->refoclk);
1342 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1347 ret = clk_prepare_enable(inno->sysclk);
1349 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1357 ret = clk_prepare_enable(inno->refpclk);
1359 dev_err(inno->dev, "failed to enable refpclk\n");
1360 clk_disable_unprepare(inno->sysclk);
1364 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1365 inno);
1369 inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1371 if (IS_ERR(inno->regmap))
1372 return PTR_ERR(inno->regmap);
1375 inno->irq = platform_get_irq(pdev, 0);
1376 if (inno->irq > 0) {
1377 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1381 dev_name(inno->dev), inno);
1386 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1387 if (IS_ERR(inno->phy)) {
1388 dev_err(inno->dev, "failed to create HDMI PHY\n");
1389 return PTR_ERR(inno->phy);
1392 phy_set_drvdata(inno->phy, inno);
1393 phy_set_bus_width(inno->phy, 8);
1395 if (inno->plat_data->ops->init) {
1396 ret = inno->plat_data->ops->init(inno);
1401 ret = inno_hdmi_phy_clk_register(inno);
1405 phy_provider = devm_of_phy_provider_register(inno->dev,
1430 .name = "inno-hdmi-phy",