Lines Matching defs:rate
555 unsigned long rate)
566 return (u64)rate * bus_width / 8;
568 return rate;
677 unsigned long rate)
680 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
683 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
747 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
753 unsigned long rate,
758 rate = (rate / 1000) * 1000;
761 if (cfg->pixclock == rate && !cfg->fracdiv)
771 unsigned long rate,
776 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
780 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
781 __func__, rate, tmdsclock);
783 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
786 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
827 inno->pixclock = rate;
903 dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
910 unsigned long rate,
915 rate = (rate / 1000) * 1000;
918 if (cfg->pixclock == rate)
928 unsigned long rate,
933 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
937 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
938 __func__, rate, tmdsclock);
940 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
943 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
981 inno->pixclock = rate;