Lines Matching defs:inno_update_bits
544 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
598 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
600 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
705 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
713 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
791 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
794 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
801 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
805 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
809 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
817 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
855 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
863 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
947 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
951 inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
971 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
1042 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
1046 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
1062 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
1064 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1070 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
1072 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
1077 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1082 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1084 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
1091 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1093 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
1095 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
1109 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
1115 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
1116 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
1117 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
1177 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1178 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1203 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1213 inno_update_bits(inno, 0xc5,
1220 inno_update_bits(inno, 0xc8,
1227 inno_update_bits(inno, 0xc9 + v,
1232 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1233 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1235 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1249 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1261 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1262 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1263 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,