Lines Matching refs:inno
284 static void phy_update_bits(struct inno_dsidphy *inno,
290 orig = readl(inno->phy_base + reg);
293 writel(tmp, inno->phy_base + reg);
296 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
299 unsigned long prate = clk_get_rate(inno->ref_clk);
358 inno->pll.prediv = best_prediv;
359 inno->pll.fbdiv = best_fbdiv;
360 inno->pll.rate = best_freq;
366 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
368 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
376 timings = inno->pdata->inno_mipi_dphy_timing_table;
378 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
381 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
384 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
386 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
388 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
390 if (inno->pdata->max_rate == MAX_2_5GHZ) {
391 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
393 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
398 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
402 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
408 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
411 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
414 txbyteclkhs = inno->pll.rate / 8;
456 for (i = 0; i < inno->pdata->num_timings; i++)
457 if (inno->pll.rate <= timings[i].rate)
460 if (i == inno->pdata->num_timings)
467 if (inno->pdata->max_rate == MAX_1GHZ) {
486 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
488 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
490 if (inno->pdata->max_rate == MAX_2_5GHZ)
491 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
493 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
495 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
497 if (inno->pdata->max_rate == MAX_2_5GHZ)
498 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
500 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
502 if (inno->pdata->max_rate == MAX_2_5GHZ)
503 phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK,
505 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
507 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
509 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
511 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
513 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
515 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
517 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
522 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
527 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
533 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
539 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
542 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
544 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
546 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
548 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
550 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
557 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
561 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
565 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
569 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
573 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
581 struct inno_dsidphy *inno = phy_get_drvdata(phy);
583 clk_prepare_enable(inno->pclk_phy);
584 clk_prepare_enable(inno->ref_clk);
585 pm_runtime_get_sync(inno->dev);
588 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
591 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
594 switch (inno->mode) {
596 inno_dsidphy_mipi_mode_enable(inno);
599 inno_dsidphy_lvds_mode_enable(inno);
610 struct inno_dsidphy *inno = phy_get_drvdata(phy);
612 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
613 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
616 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
618 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
621 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
622 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
625 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
629 pm_runtime_put(inno->dev);
630 clk_disable_unprepare(inno->ref_clk);
631 clk_disable_unprepare(inno->pclk_phy);
639 struct inno_dsidphy *inno = phy_get_drvdata(phy);
644 inno->mode = mode;
656 struct inno_dsidphy *inno = phy_get_drvdata(phy);
659 if (inno->mode != PHY_MODE_MIPI_DPHY)
666 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
694 struct inno_dsidphy *inno;
699 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
700 if (!inno)
703 inno->dev = dev;
704 inno->pdata = of_device_get_match_data(inno->dev);
705 platform_set_drvdata(pdev, inno);
707 inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
708 if (IS_ERR(inno->phy_base))
709 return PTR_ERR(inno->phy_base);
711 inno->ref_clk = devm_clk_get(dev, "ref");
712 if (IS_ERR(inno->ref_clk)) {
713 ret = PTR_ERR(inno->ref_clk);
718 inno->pclk_phy = devm_clk_get(dev, "pclk");
719 if (IS_ERR(inno->pclk_phy)) {
720 ret = PTR_ERR(inno->pclk_phy);
725 inno->rst = devm_reset_control_get(dev, "apb");
726 if (IS_ERR(inno->rst)) {
727 ret = PTR_ERR(inno->rst);
739 phy_set_drvdata(phy, inno);
755 struct inno_dsidphy *inno = platform_get_drvdata(pdev);
757 pm_runtime_disable(inno->dev);
783 .name = "inno-dsidphy",