Lines Matching defs:phy_update_bits
284 static void phy_update_bits(struct inno_dsidphy *inno,
381 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
384 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
386 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
388 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
391 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
393 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
398 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
402 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
408 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
411 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
486 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
488 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
491 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
493 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
495 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
498 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
500 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
503 phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK,
505 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
507 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
509 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
511 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
513 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
515 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
517 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
522 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
533 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
539 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
542 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
544 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
546 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
548 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
550 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
557 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
561 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
565 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
569 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
573 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
588 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
591 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
612 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
613 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
616 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
618 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
621 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
622 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
625 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,