Lines Matching refs:value
288 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
380 * to value
384 u8 value;
419 * @cell: nvmem cell containing phy tuning value
513 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
518 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
523 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
528 or->hstx_trim.value << HSTX_TRIM_SHIFT,
533 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
537 if (or->preemphasis_width.value ==
550 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
555 * Fetches HS Tx tuning value from nvmem and sets the
557 * For error case, skip setting the value and use the default value.
571 * If efuse register shows value as 0x0 (indicating value is not
573 * then use default value for high nibble that we have already
578 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
584 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
588 /* Fused TUNE1/2 value is the higher nibble only */
774 /* save reset value to override reference clock scheme later */
784 /* Set efuse value for tuning the PHY */
797 * value hardcoded in the configuration.
965 u32 value;
1021 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
1024 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
1025 &value)) {
1026 or->imp_res_offset.value = (u8)value;
1030 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
1031 &value)) {
1032 or->bias_ctrl.value = (u8)value;
1036 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
1037 &value)) {
1038 or->charge_ctrl.value = (u8)value;
1042 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
1043 &value)) {
1044 or->hstx_trim.value = (u8)value;
1049 &value)) {
1050 or->preemphasis.value = (u8)value;
1055 &value)) {
1056 or->preemphasis_width.value = (u8)value;
1060 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
1061 &value)) {
1062 or->hsdisc_trim.value = (u8)value;