Lines Matching defs:qphy
506 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
508 const struct qusb2_phy_cfg *cfg = qphy->cfg;
509 struct override_params *or = &qphy->overrides;
512 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
517 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
522 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
527 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
532 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
539 qusb2_setbits(qphy->base,
543 qusb2_clrbits(qphy->base,
549 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
559 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
561 struct device *dev = &qphy->phy->dev;
562 const struct qusb2_phy_cfg *cfg = qphy->cfg;
566 if (!qphy->cell)
576 val = nvmem_cell_read(qphy->cell, NULL);
590 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
593 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
600 struct qusb2_phy *qphy = phy_get_drvdata(phy);
602 qphy->mode = mode;
609 struct qusb2_phy *qphy = dev_get_drvdata(dev);
610 const struct qusb2_phy_cfg *cfg = qphy->cfg;
613 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
615 if (!qphy->phy_initialized) {
627 switch (qphy->mode) {
645 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
649 qusb2_setbits(qphy->base,
656 if (qphy->mode != PHY_MODE_INVALID) {
657 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
660 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
664 if (!qphy->has_se_clk_scheme)
665 clk_disable_unprepare(qphy->ref_clk);
667 clk_disable_unprepare(qphy->cfg_ahb_clk);
668 clk_disable_unprepare(qphy->iface_clk);
675 struct qusb2_phy *qphy = dev_get_drvdata(dev);
676 const struct qusb2_phy_cfg *cfg = qphy->cfg;
679 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
681 if (!qphy->phy_initialized) {
686 ret = clk_prepare_enable(qphy->iface_clk);
692 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
698 if (!qphy->has_se_clk_scheme) {
699 ret = clk_prepare_enable(qphy->ref_clk);
706 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
710 qusb2_clrbits(qphy->base,
718 clk_disable_unprepare(qphy->cfg_ahb_clk);
720 clk_disable_unprepare(qphy->iface_clk);
727 struct qusb2_phy *qphy = phy_get_drvdata(phy);
728 const struct qusb2_phy_cfg *cfg = qphy->cfg;
736 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
740 ret = clk_prepare_enable(qphy->iface_clk);
747 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
754 ret = reset_control_assert(qphy->phy_reset);
763 ret = reset_control_deassert(qphy->phy_reset);
770 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
771 qphy->cfg->disable_ctrl);
775 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
778 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
782 qusb2_phy_override_phy_params(qphy);
785 qusb2_phy_set_tune2_param(qphy);
788 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
799 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
807 if (qphy->tcsr) {
808 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
819 qphy->has_se_clk_scheme = false;
826 if (!qphy->has_se_clk_scheme) {
827 ret = clk_prepare_enable(qphy->ref_clk);
836 if (!qphy->has_se_clk_scheme)
841 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
844 readl(qphy->base + QUSB2PHY_PLL_TEST);
850 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
857 qphy->phy_initialized = true;
862 if (!qphy->has_se_clk_scheme)
863 clk_disable_unprepare(qphy->ref_clk);
865 reset_control_assert(qphy->phy_reset);
867 clk_disable_unprepare(qphy->cfg_ahb_clk);
869 clk_disable_unprepare(qphy->iface_clk);
871 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
878 struct qusb2_phy *qphy = phy_get_drvdata(phy);
881 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
882 qphy->cfg->disable_ctrl);
884 if (!qphy->has_se_clk_scheme)
885 clk_disable_unprepare(qphy->ref_clk);
887 reset_control_assert(qphy->phy_reset);
889 clk_disable_unprepare(qphy->cfg_ahb_clk);
890 clk_disable_unprepare(qphy->iface_clk);
892 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
894 qphy->phy_initialized = false;
960 struct qusb2_phy *qphy;
968 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
969 if (!qphy)
971 or = &qphy->overrides;
973 qphy->base = devm_platform_ioremap_resource(pdev, 0);
974 if (IS_ERR(qphy->base))
975 return PTR_ERR(qphy->base);
977 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
978 if (IS_ERR(qphy->cfg_ahb_clk))
979 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk),
982 qphy->ref_clk = devm_clk_get(dev, "ref");
983 if (IS_ERR(qphy->ref_clk))
984 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk),
987 qphy->iface_clk = devm_clk_get_optional(dev, "iface");
988 if (IS_ERR(qphy->iface_clk))
989 return PTR_ERR(qphy->iface_clk);
991 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
992 if (IS_ERR(qphy->phy_reset)) {
994 return PTR_ERR(qphy->phy_reset);
997 num = ARRAY_SIZE(qphy->vregs);
999 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
1001 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
1007 qphy->cfg = of_device_get_match_data(dev);
1009 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
1011 if (IS_ERR(qphy->tcsr)) {
1013 qphy->tcsr = NULL;
1016 qphy->cell = devm_nvmem_cell_get(dev, NULL);
1017 if (IS_ERR(qphy->cell)) {
1018 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
1020 qphy->cell = NULL;
1081 qphy->phy = generic_phy;
1083 dev_set_drvdata(dev, qphy);
1084 phy_set_drvdata(generic_phy, qphy);