Lines Matching refs:qmp
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
32 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
33 #include "phy-qcom-qmp-pcie-qhp.h"
3116 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3118 const struct qmp_phy_cfg *cfg = qmp->cfg;
3122 tx3 = qmp->port_b + offs->tx;
3123 rx3 = qmp->port_b + offs->rx;
3124 tx4 = qmp->port_b + offs->tx2;
3125 rx4 = qmp->port_b + offs->rx2;
3134 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3136 const struct qmp_phy_cfg *cfg = qmp->cfg;
3137 void __iomem *serdes = qmp->serdes;
3138 void __iomem *tx = qmp->tx;
3139 void __iomem *rx = qmp->rx;
3140 void __iomem *tx2 = qmp->tx2;
3141 void __iomem *rx2 = qmp->rx2;
3142 void __iomem *pcs = qmp->pcs;
3143 void __iomem *pcs_misc = qmp->pcs_misc;
3144 void __iomem *ln_shrd = qmp->ln_shrd;
3162 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3164 qmp_pcie_init_port_b(qmp, tbls);
3172 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3173 const struct qmp_phy_cfg *cfg = qmp->cfg;
3176 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3178 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3182 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3184 dev_err(qmp->dev, "reset assert failed\n");
3188 ret = reset_control_assert(qmp->nocsr_reset);
3190 dev_err(qmp->dev, "no-csr reset assert failed\n");
3196 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
3198 dev_err(qmp->dev, "reset deassert failed\n");
3202 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3209 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3211 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3218 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3219 const struct qmp_phy_cfg *cfg = qmp->cfg;
3221 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3223 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3225 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3232 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3233 const struct qmp_phy_cfg *cfg = qmp->cfg;
3235 void __iomem *pcs = qmp->pcs;
3243 if (qmp->mode == PHY_MODE_PCIE_RC)
3248 qmp_pcie_init_registers(qmp, &cfg->tbls);
3249 qmp_pcie_init_registers(qmp, mode_tbls);
3251 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
3255 ret = reset_control_deassert(qmp->nocsr_reset);
3257 dev_err(qmp->dev, "no-csr reset deassert failed\n");
3275 dev_err(qmp->dev, "phy initialization timed-out\n");
3282 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3289 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3290 const struct qmp_phy_cfg *cfg = qmp->cfg;
3292 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3295 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3298 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
3302 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3336 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3341 qmp->mode = submode;
3358 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
3360 const struct qmp_phy_cfg *cfg = qmp->cfg;
3361 struct device *dev = qmp->dev;
3365 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3366 if (!qmp->vregs)
3370 qmp->vregs[i].supply = cfg->vreg_list[i];
3372 return devm_regulator_bulk_get(dev, num, qmp->vregs);
3375 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
3377 const struct qmp_phy_cfg *cfg = qmp->cfg;
3378 struct device *dev = qmp->dev;
3382 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3383 sizeof(*qmp->resets), GFP_KERNEL);
3384 if (!qmp->resets)
3388 qmp->resets[i].id = cfg->reset_list[i];
3390 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3395 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
3396 if (IS_ERR(qmp->nocsr_reset))
3397 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
3404 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
3406 struct device *dev = qmp->dev;
3410 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3411 if (!qmp->clks)
3415 qmp->clks[i].id = qmp_pciephy_clk_l[i];
3417 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3443 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
3445 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3451 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
3461 if (qmp->cfg->pipe_clock_rate)
3462 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
3468 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
3480 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
3483 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
3485 struct platform_device *pdev = to_platform_device(qmp->dev);
3486 const struct qmp_phy_cfg *cfg = qmp->cfg;
3487 struct device *dev = qmp->dev;
3490 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3491 if (IS_ERR(qmp->serdes))
3492 return PTR_ERR(qmp->serdes);
3500 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3501 if (IS_ERR(qmp->tx))
3502 return PTR_ERR(qmp->tx);
3505 qmp->rx = qmp->tx;
3507 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3508 if (IS_ERR(qmp->rx))
3509 return PTR_ERR(qmp->rx);
3511 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3512 if (IS_ERR(qmp->pcs))
3513 return PTR_ERR(qmp->pcs);
3516 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3517 if (IS_ERR(qmp->tx2))
3518 return PTR_ERR(qmp->tx2);
3520 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3521 if (IS_ERR(qmp->rx2))
3522 return PTR_ERR(qmp->rx2);
3524 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3526 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
3529 if (IS_ERR(qmp->pcs_misc) &&
3530 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
3531 qmp->pcs_misc = qmp->pcs + 0x400;
3533 if (IS_ERR(qmp->pcs_misc)) {
3537 return PTR_ERR(qmp->pcs_misc);
3547 qmp->num_pipe_clks = 1;
3548 qmp->pipe_clks[0].id = "pipe";
3549 qmp->pipe_clks[0].clk = clk;
3554 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
3560 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
3568 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
3574 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
3578 qmp->tcsr_4ln_config = ret;
3580 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
3585 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
3587 struct platform_device *pdev = to_platform_device(qmp->dev);
3588 const struct qmp_phy_cfg *cfg = qmp->cfg;
3590 struct device *dev = qmp->dev;
3597 ret = qmp_pcie_get_4ln_config(qmp);
3605 qmp->serdes = base + offs->serdes;
3606 qmp->pcs = base + offs->pcs;
3607 qmp->pcs_misc = base + offs->pcs_misc;
3608 qmp->tx = base + offs->tx;
3609 qmp->rx = base + offs->rx;
3612 qmp->tx2 = base + offs->tx2;
3613 qmp->rx2 = base + offs->rx2;
3616 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3617 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
3618 if (IS_ERR(qmp->port_b))
3619 return PTR_ERR(qmp->port_b);
3623 qmp->ln_shrd = base + offs->ln_shrd;
3625 qmp->num_pipe_clks = 2;
3626 qmp->pipe_clks[0].id = "pipe";
3627 qmp->pipe_clks[1].id = "pipediv2";
3629 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
3633 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
3645 struct qmp_pcie *qmp;
3648 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3649 if (!qmp)
3652 qmp->dev = dev;
3654 qmp->cfg = of_device_get_match_data(dev);
3655 if (!qmp->cfg)
3658 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
3659 WARN_ON_ONCE(!qmp->cfg->phy_status);
3661 ret = qmp_pcie_clk_init(qmp);
3665 ret = qmp_pcie_reset_init(qmp);
3669 ret = qmp_pcie_vreg_init(qmp);
3676 ret = qmp_pcie_parse_dt_legacy(qmp, np);
3679 ret = qmp_pcie_parse_dt(qmp);
3684 ret = phy_pipe_clk_register(qmp, np);
3688 qmp->mode = PHY_MODE_PCIE_RC;
3690 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
3691 if (IS_ERR(qmp->phy)) {
3692 ret = PTR_ERR(qmp->phy);
3697 phy_set_drvdata(qmp->phy, qmp);
3712 .compatible = "qcom,ipq6018-qmp-pcie-phy",
3715 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
3718 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3721 .compatible = "qcom,msm8998-qmp-pcie-phy",
3724 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
3727 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
3730 .compatible = "qcom,sc8180x-qmp-pcie-phy",
3733 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
3736 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
3739 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
3745 .compatible = "qcom,sdm845-qmp-pcie-phy",
3748 .compatible = "qcom,sdx55-qmp-pcie-phy",
3751 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
3754 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
3757 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
3760 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3763 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
3766 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3769 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3772 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3775 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3778 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3781 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3784 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3794 .name = "qcom-qmp-pcie-phy",