Lines Matching refs:phy_dwc3
137 * @phy_dwc3: QCOM DWC3 phy context
142 static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
146 u32 write_val, tmp = readl(phy_dwc3->base + offset);
151 writel(write_val, phy_dwc3->base + offset);
154 tmp = readl(phy_dwc3->base + offset);
158 dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
171 * @phy_dwc3: QCOM DWC3 phy context
175 static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
180 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
182 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
184 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
188 writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
190 phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
192 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
196 writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
198 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
202 dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
209 * @phy_dwc3: QCOM DWC3 phy context
213 static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
218 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
220 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
222 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
231 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
233 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
238 readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
240 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
242 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
246 *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
254 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
258 ret = clk_prepare_enable(phy_dwc3->xo_clk);
262 ret = clk_prepare_enable(phy_dwc3->ref_clk);
264 clk_disable_unprepare(phy_dwc3->xo_clk);
279 if (!phy_dwc3->xo_clk)
282 writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
286 writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
293 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
295 clk_disable_unprepare(phy_dwc3->ref_clk);
296 clk_disable_unprepare(phy_dwc3->xo_clk);
303 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
307 ret = clk_prepare_enable(phy_dwc3->xo_clk);
311 ret = clk_prepare_enable(phy_dwc3->ref_clk);
313 clk_disable_unprepare(phy_dwc3->xo_clk);
318 data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
320 phy_dwc3->base + SSUSB_PHY_CTRL_REG);
322 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
325 if (!phy_dwc3->xo_clk)
330 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
336 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
343 ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
348 ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
352 ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
358 ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
369 ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
376 data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
378 ret = usb_ss_write_phycreg(phy_dwc3,
389 ret = usb_ss_read_phycreg(phy_dwc3,
395 data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
399 ret = usb_ss_write_phycreg(phy_dwc3,
406 data |= SSPHY_MPLL(phy_dwc3->mpll);
407 usb_ss_write_phycreg(phy_dwc3, 0x30, data);
416 data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
422 PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
425 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
434 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
441 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
443 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
445 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
448 clk_disable_unprepare(phy_dwc3->ref_clk);
449 clk_disable_unprepare(phy_dwc3->xo_clk);
486 struct usb_phy *phy_dwc3;
490 phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
491 if (!phy_dwc3)
496 phy_dwc3->dev = &pdev->dev;
502 phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
504 if (!phy_dwc3->base) {
505 dev_err(phy_dwc3->dev, "failed to map reg\n");
509 phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
510 if (IS_ERR(phy_dwc3->ref_clk)) {
511 dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
512 return PTR_ERR(phy_dwc3->ref_clk);
515 clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
517 phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
518 if (IS_ERR(phy_dwc3->xo_clk)) {
519 dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
520 phy_dwc3->xo_clk = NULL;
525 &phy_dwc3->rx_eq))
526 phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
529 &phy_dwc3->tx_deamp_3_5db))
530 phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
532 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
533 phy_dwc3->mpll = SSPHY_MPLL_VALUE;
535 generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
540 phy_set_drvdata(generic_phy, phy_dwc3);
541 platform_set_drvdata(pdev, phy_dwc3);
543 phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,