Lines Matching refs:base
119 void __iomem *base;
146 u32 write_val, tmp = readl(phy_dwc3->base + offset);
151 writel(write_val, phy_dwc3->base + offset);
154 tmp = readl(phy_dwc3->base + offset);
180 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
182 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
184 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
188 writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
190 phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
192 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
196 writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
198 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
218 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
220 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
222 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
231 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
233 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
238 readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
240 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
242 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
246 *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
282 writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
286 writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
318 data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
320 phy_dwc3->base + SSUSB_PHY_CTRL_REG);
322 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
330 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
336 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
416 data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
502 phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
504 if (!phy_dwc3->base) {