Lines Matching refs:tx1
89 void __iomem *tx1;
270 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
271 writel(swing, edp->tx1 + TXn_TX_DRV_LVL);
272 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);
474 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
476 writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
500 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
501 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);
502 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);
503 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
504 writel(0x04, edp->tx1 + TXn_TX_BAND);
526 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);
527 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);
528 writel(0x00, edp->tx1 + TXn_TX_POL_INV);
530 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);
533 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);
534 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);
537 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);
539 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);
563 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);
564 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
793 edp->tx1 = devm_platform_ioremap_resource(pdev, 2);
794 if (IS_ERR(edp->tx1))
795 return PTR_ERR(edp->tx1);