Lines Matching defs:edp
87 void __iomem *edp;
175 struct qcom_edp *edp = phy_get_drvdata(phy);
176 const struct qcom_edp_cfg *cfg = edp->cfg;
180 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies);
184 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks);
190 edp->edp + DP_PHY_PD_CTL);
193 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
195 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);
201 edp->edp + DP_PHY_PD_CTL);
208 writel(0xfc, edp->edp + DP_PHY_MODE);
210 writel(0x00, edp->edp + DP_PHY_AUX_CFG0);
211 writel(0x13, edp->edp + DP_PHY_AUX_CFG1);
212 writel(0x24, edp->edp + DP_PHY_AUX_CFG2);
213 writel(0x00, edp->edp + DP_PHY_AUX_CFG3);
214 writel(0x0a, edp->edp + DP_PHY_AUX_CFG4);
215 writel(0x26, edp->edp + DP_PHY_AUX_CFG5);
216 writel(0x0a, edp->edp + DP_PHY_AUX_CFG6);
217 writel(0x03, edp->edp + DP_PHY_AUX_CFG7);
218 writel(cfg8, edp->edp + DP_PHY_AUX_CFG8);
219 writel(0x03, edp->edp + DP_PHY_AUX_CFG9);
223 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK);
230 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies);
235 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts)
237 const struct qcom_edp_cfg *cfg = edp->cfg;
266 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
267 writel(swing, edp->tx0 + TXn_TX_DRV_LVL);
268 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);
270 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
271 writel(swing, edp->tx1 + TXn_TX_DRV_LVL);
272 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);
280 struct qcom_edp *edp = phy_get_drvdata(phy);
283 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts));
286 ret = qcom_edp_set_voltages(edp, dp_opts);
291 static int qcom_edp_configure_ssc(const struct qcom_edp *edp)
293 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
315 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER);
316 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1);
317 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1);
318 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2);
319 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0);
320 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0);
325 static int qcom_edp_configure_pll(const struct qcom_edp *edp)
327 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
377 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL);
378 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL);
379 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL);
380 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1);
381 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE);
382 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT);
383 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL);
384 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO);
385 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN);
386 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0);
387 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0);
388 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0);
389 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0);
390 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0);
391 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0);
392 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0);
393 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG);
394 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0);
395 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0);
396 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP);
397 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0);
398 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0);
400 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER);
401 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0);
402 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL);
403 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
404 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN);
405 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0);
406 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0);
411 static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq)
413 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
442 writel(vco_div, edp->edp + DP_PHY_VCO_DIV);
449 const struct qcom_edp *edp = phy_get_drvdata(phy);
450 const struct qcom_edp_cfg *cfg = edp->cfg;
462 edp->edp + DP_PHY_PD_CTL);
463 writel(0xfc, edp->edp + DP_PHY_MODE);
465 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS,
473 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
474 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
475 writel(0x00, edp->tx0 + TXn_LANE_MODE_1);
476 writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
478 if (edp->dp_opts.ssc) {
479 ret = qcom_edp_configure_ssc(edp);
484 ret = qcom_edp_configure_pll(edp);
489 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL);
490 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL);
493 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
494 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);
495 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);
496 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);
497 writel(0x04, edp->tx0 + TXn_TX_BAND);
500 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
501 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);
502 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);
503 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
504 writel(0x04, edp->tx1 + TXn_TX_BAND);
506 ret = qcom_edp_set_vco_div(edp, &pixel_freq);
510 writel(0x01, edp->edp + DP_PHY_CFG);
511 writel(0x05, edp->edp + DP_PHY_CFG);
512 writel(0x01, edp->edp + DP_PHY_CFG);
513 writel(0x09, edp->edp + DP_PHY_CFG);
515 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL);
517 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS,
522 writel(0x19, edp->edp + DP_PHY_CFG);
523 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);
524 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);
525 writel(0x00, edp->tx0 + TXn_TX_POL_INV);
526 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);
527 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);
528 writel(0x00, edp->tx1 + TXn_TX_POL_INV);
529 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);
530 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);
531 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);
532 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);
533 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);
534 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);
536 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);
537 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);
538 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);
539 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);
541 if (edp->dp_opts.lanes == 1) {
547 } else if (edp->dp_opts.lanes == 2) {
561 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN);
562 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
563 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);
564 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
565 writel(cfg1, edp->edp + DP_PHY_CFG_1);
567 writel(0x18, edp->edp + DP_PHY_CFG);
570 writel(0x19, edp->edp + DP_PHY_CFG);
572 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS,
577 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000);
578 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq);
585 const struct qcom_edp *edp = phy_get_drvdata(phy);
587 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);
594 struct qcom_edp *edp = phy_get_drvdata(phy);
596 clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks);
597 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies);
677 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_pixel_hw);
678 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
717 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_link_hw);
718 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
737 static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np)
744 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL);
749 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev));
752 edp->dp_link_hw.init = &init;
753 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw);
757 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev));
760 edp->dp_pixel_hw.init = &init;
761 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw);
765 data->hws[0] = &edp->dp_link_hw;
766 data->hws[1] = &edp->dp_pixel_hw;
768 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data);
775 struct qcom_edp *edp;
778 edp = devm_kzalloc(dev, sizeof(*edp), GFP_KERNEL);
779 if (!edp)
782 edp->dev = dev;
783 edp->cfg = of_device_get_match_data(&pdev->dev);
785 edp->edp = devm_platform_ioremap_resource(pdev, 0);
786 if (IS_ERR(edp->edp))
787 return PTR_ERR(edp->edp);
789 edp->tx0 = devm_platform_ioremap_resource(pdev, 1);
790 if (IS_ERR(edp->tx0))
791 return PTR_ERR(edp->tx0);
793 edp->tx1 = devm_platform_ioremap_resource(pdev, 2);
794 if (IS_ERR(edp->tx1))
795 return PTR_ERR(edp->tx1);
797 edp->pll = devm_platform_ioremap_resource(pdev, 3);
798 if (IS_ERR(edp->pll))
799 return PTR_ERR(edp->pll);
801 edp->clks[0].id = "aux";
802 edp->clks[1].id = "cfg_ahb";
803 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks);
807 edp->supplies[0].supply = "vdda-phy";
808 edp->supplies[1].supply = "vdda-pll";
809 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies);
813 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */
815 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply);
819 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */
821 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply);
825 ret = qcom_edp_clks_register(edp, pdev->dev.of_node);
829 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops);
830 if (IS_ERR(edp->phy)) {
832 return PTR_ERR(edp->phy);
835 phy_set_drvdata(edp->phy, edp);
842 { .compatible = "qcom,sc7280-edp-phy" },
843 { .compatible = "qcom,sc8180x-edp-phy" },
845 { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg },
853 .name = "qcom-edp-phy",