Lines Matching defs:params

718 				      struct sparx5_sd25g28_params *params)
821 *params = init;
828 struct sparx5_sd10g28_params *params)
927 *params = init;
1147 struct sparx5_sd25g28_params *params,
1150 if (params->reg_rst == 1) {
1164 struct sparx5_sd25g28_params *params)
1183 (params->r_d_width_ctrl_from_hwt) |
1184 SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
1191 (params->cfg_common_reserve_7_0),
1196 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
1202 (params->cfg_pll_reserve_3_0),
1207 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
1213 (params->l0_cfg_tx_reserve_15_8),
1219 (params->l0_cfg_tx_reserve_7_0),
1254 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0),
1260 (params->r_txfifo_ck_div_pmad_2_0) |
1262 (params->r_rxfifo_ck_div_pmad_2_0),
1268 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) |
1270 (params->cfg_vco_div_mode_1_0),
1277 (params->cfg_pre_divsel_1_0),
1282 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0),
1293 (params->cfg_pma_tx_ck_bitwidth_2_0),
1299 (params->cfg_tx_prediv_1_0),
1305 (params->cfg_rxdiv_sel_2_0),
1311 (params->cfg_tx_subrate_2_0),
1317 (params->cfg_rx_subrate_2_0),
1322 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
1328 (params->cfg_dfetap_en_5_1),
1333 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
1338 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en),
1343 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd),
1349 (params->cfg_itx_ipdriver_base_2_0),
1354 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0),
1359 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0),
1364 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) |
1365 SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly),
1372 (params->cfg_tx_reserve_15_8),
1378 (params->cfg_tx_reserve_7_0),
1383 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0),
1389 (params->cfg_txcal_man_en),
1395 (params->cfg_txcal_shift_code_5_0),
1401 (params->cfg_txcal_valid_sel_3_0),
1406 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0),
1411 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0),
1416 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0),
1422 (params->cfg_dis_2ndorder),
1427 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn),
1433 (params->cfg_itx_ipcml_base_1_0),
1439 (params->cfg_rx_reserve_7_0),
1445 (params->cfg_rx_reserve_15_8),
1450 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) |
1451 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0),
1458 (params->cfg_vga_ctrl_byp_4_0),
1464 (params->cfg_eqr_force_3_0),
1470 (params->cfg_eqc_force_3_0) |
1471 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd),
1478 (params->cfg_sum_setcm_en),
1484 (params->cfg_init_pos_iscan_6_0),
1490 (params->cfg_init_pos_ipi_6_0),
1495 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
1501 (params->cfg_dfedig_m_2_0),
1506 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig),
1511 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) |
1512 SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv),
1518 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) |
1519 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en),
1525 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en),
1530 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en),
1605 (params->cfg_alos_thr_2_0),
1638 struct sparx5_sd10g28_params *params)
1650 if (params->skip_cmu_cfg)
1653 cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index);
1658 if (params->is_6g)
1706 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) |
1707 SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel),
1714 (params->cfg_lane_reserve_7_0),
1720 (params->cfg_ssc_rtl_clk_sel),
1726 (params->cfg_txrate_1_0) |
1728 (params->cfg_rxrate_1_0),
1735 (params->r_d_width_ctrl_2_0),
1741 (params->cfg_pma_tx_ck_bitwidth_2_0),
1747 (params->cfg_rxdiv_sel_2_0),
1753 (params->r_pcs2pma_phymode_4_0),
1758 sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
1764 (params->cfg_dfeck_en) |
1765 SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) |
1767 (params->cfg_erramp_pd),
1775 (params->cfg_dfetap_en_5_1),
1781 (params->cfg_pi_DFE_en),
1786 sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |
1787 SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) |
1788 SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) |
1790 (params->cfg_tap_adv_3_0),
1798 sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),
1804 (params->cfg_tap_dly_4_0),
1810 (params->cfg_vga_ctrl_3_0),
1816 (params->cfg_vga_cp_2_0),
1822 (params->cfg_eq_res_3_0),
1827 sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),
1833 (params->cfg_eq_c_force_3_0) |
1835 (params->cfg_sum_setcm_en),
1842 (params->cfg_en_dfedig),
1848 (params->cfg_en_preemph),
1854 (params->cfg_itx_ippreemp_base_1_0) |
1856 (params->cfg_itx_ipdriver_base_2_0),
1863 (params->cfg_ibias_tune_reserve_5_0),
1869 (params->cfg_txswing_half),
1875 (params->cfg_dis_2nd_order),
1881 (params->cfg_rx_ssc_lh),
1887 (params->cfg_pi_floop_steps_1_0),
1893 (params->cfg_pi_ext_dac_23_16),
1899 (params->cfg_pi_ext_dac_15_8),
1905 (params->cfg_iscan_ext_dac_7_0),
1911 (params->cfg_cdr_kf_gen1_2_0),
1917 (params->r_cdr_m_gen1_7_0),
1923 (params->cfg_pi_bw_gen1_3_0),
1929 (params->cfg_pi_ext_dac_7_0),
1934 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),
1940 (params->cfg_mp_max_3_0),
1946 (params->cfg_rstn_dfedig),
1952 (params->cfg_alos_thr_3_0),
1958 (params->cfg_predrv_slewrate_1_0),
1964 (params->cfg_itx_ipcml_base_1_0),
1970 (params->cfg_ip_pre_base_1_0),
1976 (params->cfg_lane_reserve_15_8),
1982 (params->r_en_auto_cdr_rstn),
1988 (params->cfg_oscal_afe) |
1990 (params->cfg_pd_osdac_afe),
1997 (params->cfg_resetb_oscal_afe[0]),
2003 (params->cfg_resetb_oscal_afe[1]),
2009 (params->r_tx_pol_inv) |
2011 (params->r_rx_pol_inv),
2018 (params->cfg_rx2tx_lp_en) |
2020 (params->cfg_tx2rx_lp_en),
2026 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |
2027 SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en),
2048 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100),
2053 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100),
2058 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100),
2096 struct sparx5_sd25g28_params params;
2102 sparx5_sd25g28_get_params(macro, &media, &mode, &args, &params);
2103 sparx5_sd25g28_reset(macro->priv->regs, &params, macro->stpidx);
2104 return sparx5_sd25g28_apply_params(macro, &params);
2111 struct sparx5_sd10g28_params params;
2125 sparx5_sd10g28_get_params(macro, &media, &mode, &args, &params);
2127 return sparx5_sd10g28_apply_params(macro, &params);