Lines Matching defs:ret_val
297 struct lan966x_sd6g40_mode_args *ret_val)
301 ret_val->lane_10bit_sel = 0;
303 ret_val->mpll_multiplier = 40;
304 ret_val->ref_clkdiv2 = 0x1;
305 ret_val->tx_rate = 0x0;
306 ret_val->rx_rate = 0x0;
308 ret_val->mpll_multiplier = 100;
309 ret_val->ref_clkdiv2 = 0x0;
310 ret_val->tx_rate = 0x0;
311 ret_val->rx_rate = 0x0;
316 ret_val->lane_10bit_sel = 1;
318 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 50 : 40;
319 ret_val->ref_clkdiv2 = 0x1;
320 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
321 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
323 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 125 : 100;
324 ret_val->ref_clkdiv2 = 0x0;
325 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
326 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
339 struct lan966x_sd6g40_setup *ret_val)
350 ret_val->lane_10bit_sel = mode_args->lane_10bit_sel;
351 ret_val->rx_rate = mode_args->rx_rate;
352 ret_val->tx_rate = mode_args->tx_rate;
353 ret_val->mpll_multiplier = mode_args->mpll_multiplier;
354 ret_val->ref_clkdiv2 = mode_args->ref_clkdiv2;
355 ret_val->rx_term_en = 0;
358 ret_val->lane_loopbk_en = 1;
360 ret_val->lane_loopbk_en = 0;
362 ret_val->tx_invert = !!config.txinvert;
363 ret_val->rx_invert = !!config.rxinvert;