Lines Matching refs:phyd
302 void __iomem *phyd; /* include u3phyd_bank2 */
534 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
546 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
552 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
579 void __iomem *phyd = u3_banks->phyd;
594 mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV,
604 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val);
605 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
609 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val);
610 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
769 void __iomem *phyd = u3_banks->phyd;
782 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
787 mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);
789 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);
791 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);
984 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
987 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
1024 void __iomem *phyd = u3_banks->phyd;
1027 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6,
1032 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);
1034 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);
1036 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4,
1041 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4,
1046 mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);
1048 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
1053 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
1058 mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);
1060 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);
1081 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1085 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1109 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
1336 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
1338 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
1340 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
1342 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
1344 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);