Lines Matching refs:com
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
296 void __iomem *com;
381 void __iomem *com = u2_banks->com;
393 tmp = readl(com + U3P_USBPHYACR1);
399 tmp = readl(com + U3P_USBPHYACR1);
414 tmp = readl(com + U3P_USBPHYACR1);
420 tmp = readl(com + U3P_USBPHYACR6);
426 tmp = readl(com + U3P_USBPHYACR6);
453 void __iomem *com = u2_banks->com;
468 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val);
472 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val);
482 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val);
486 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val);
490 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val);
699 void __iomem *com = u2_banks->com;
713 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
757 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
761 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
800 void __iomem *com = u2_banks->com;
805 mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);
807 mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);
809 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
811 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1,
819 void __iomem *com = u2_banks->com;
823 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
825 mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
828 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
830 mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
833 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
835 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
839 mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN);
841 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
843 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
845 mtk_phy_set_bits(com + U3P_U2PHYDTM0,
851 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
853 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);
865 void __iomem *com = u2_banks->com;
869 mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
871 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
873 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
876 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
878 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
887 void __iomem *com = u2_banks->com;
891 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
893 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
895 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
898 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
900 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
910 void __iomem *com = u2_banks->com;
914 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
916 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
927 tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
942 writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
1075 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
1103 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
1150 void __iomem *com = u2_banks->com;
1153 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN);
1156 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
1160 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
1164 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
1172 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1177 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
1181 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
1331 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1671 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");