Lines Matching defs:instance
695 struct mtk_phy_instance *instance)
697 struct u2phy_banks *u2_banks = &instance->u2_banks;
709 if (instance->eye_src)
724 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
753 instance->index, fm_out, calibration_val,
765 struct mtk_phy_instance *instance)
767 struct u3phy_banks *u3_banks = &instance->u3_banks;
793 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
797 struct mtk_phy_instance *instance)
799 struct u2phy_banks *u2_banks = &instance->u2_banks;
816 struct mtk_phy_instance *instance)
818 struct u2phy_banks *u2_banks = &instance->u2_banks;
820 u32 index = instance->index;
856 u2_phy_pll_26m_set(tphy, instance);
862 struct mtk_phy_instance *instance)
864 struct u2phy_banks *u2_banks = &instance->u2_banks;
866 u32 index = instance->index;
884 struct mtk_phy_instance *instance)
886 struct u2phy_banks *u2_banks = &instance->u2_banks;
888 u32 index = instance->index;
907 struct mtk_phy_instance *instance)
909 struct u2phy_banks *u2_banks = &instance->u2_banks;
911 u32 index = instance->index;
921 struct mtk_phy_instance *instance,
924 struct u2phy_banks *u2_banks = &instance->u2_banks;
946 struct mtk_phy_instance *instance)
948 struct u3phy_banks *u3_banks = &instance->u3_banks;
992 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
996 struct mtk_phy_instance *instance)
998 struct u3phy_banks *bank = &instance->u3_banks;
1008 struct mtk_phy_instance *instance)
1011 struct u3phy_banks *bank = &instance->u3_banks;
1021 struct mtk_phy_instance *instance)
1023 struct u3phy_banks *u3_banks = &instance->u3_banks;
1062 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1066 struct mtk_phy_instance *instance)
1068 struct u2phy_banks *u2_banks = &instance->u2_banks;
1069 struct u3phy_banks *u3_banks = &instance->u3_banks;
1071 switch (instance->type) {
1075 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
1081 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1082 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
1085 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1094 struct mtk_phy_instance *instance)
1096 struct u2phy_banks *u2_banks = &instance->u2_banks;
1097 struct u3phy_banks *u3_banks = &instance->u3_banks;
1099 switch (instance->type) {
1101 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
1102 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
1103 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
1107 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
1108 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
1109 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
1110 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
1119 struct mtk_phy_instance *instance)
1121 struct device *dev = &instance->phy->dev;
1123 if (instance->type != PHY_TYPE_USB2)
1126 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
1128 &instance->eye_src);
1130 &instance->eye_vrt);
1132 &instance->eye_term);
1134 &instance->intr);
1136 &instance->discth);
1138 &instance->pre_emphasis);
1140 instance->bc12_en, instance->eye_src,
1141 instance->eye_vrt, instance->eye_term,
1142 instance->intr, instance->discth);
1143 dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
1147 struct mtk_phy_instance *instance)
1149 struct u2phy_banks *u2_banks = &instance->u2_banks;
1152 if (instance->bc12_en) /* BC1.2 path Enable */
1155 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
1157 instance->eye_src);
1159 if (instance->eye_vrt)
1161 instance->eye_vrt);
1163 if (instance->eye_term)
1165 instance->eye_term);
1167 if (instance->intr) {
1173 instance->intr);
1176 if (instance->discth)
1178 instance->discth);
1180 if (instance->pre_emphasis)
1182 instance->pre_emphasis);
1186 static int phy_type_syscon_get(struct mtk_phy_instance *instance,
1201 instance->type_sw_reg = args.args[0];
1202 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
1203 instance->type_sw = syscon_node_to_regmap(args.np);
1205 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
1206 instance->type_sw_reg, instance->type_sw_index);
1208 return PTR_ERR_OR_ZERO(instance->type_sw);
1211 static int phy_type_set(struct mtk_phy_instance *instance)
1216 if (!instance->type_sw)
1219 switch (instance->type) {
1237 offset = instance->type_sw_index * BITS_PER_BYTE;
1238 regmap_update_bits(instance->type_sw, instance->type_sw_reg,
1244 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
1246 struct device *dev = &instance->phy->dev;
1251 instance->efuse_sw_en = 0;
1256 instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
1257 if (!instance->efuse_sw_en)
1260 switch (instance->type) {
1262 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1269 if (!instance->efuse_intr) {
1271 instance->efuse_sw_en = 0;
1275 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
1280 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1286 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
1292 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
1299 if (!instance->efuse_intr &&
1300 !instance->efuse_rx_imp &&
1301 !instance->efuse_tx_imp) {
1303 instance->efuse_sw_en = 0;
1308 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
1311 dev_err(dev, "no sw efuse for type %d\n", instance->type);
1318 static void phy_efuse_set(struct mtk_phy_instance *instance)
1320 struct device *dev = &instance->phy->dev;
1321 struct u2phy_banks *u2_banks = &instance->u2_banks;
1322 struct u3phy_banks *u3_banks = &instance->u3_banks;
1324 if (!instance->efuse_sw_en)
1327 switch (instance->type) {
1332 instance->efuse_intr);
1339 instance->efuse_tx_imp);
1343 instance->efuse_rx_imp);
1347 instance->efuse_intr);
1350 dev_warn(dev, "no sw efuse for type %d\n", instance->type);
1357 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1361 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1365 phy_efuse_set(instance);
1367 switch (instance->type) {
1369 u2_phy_instance_init(tphy, instance);
1370 u2_phy_props_set(tphy, instance);
1373 u3_phy_instance_init(tphy, instance);
1376 pcie_phy_instance_init(tphy, instance);
1379 sata_phy_instance_init(tphy, instance);
1386 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1395 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1398 if (instance->type == PHY_TYPE_USB2) {
1399 u2_phy_instance_power_on(tphy, instance);
1400 hs_slew_rate_calibrate(tphy, instance);
1401 } else if (instance->type == PHY_TYPE_PCIE) {
1402 pcie_phy_instance_power_on(tphy, instance);
1410 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1413 if (instance->type == PHY_TYPE_USB2)
1414 u2_phy_instance_power_off(tphy, instance);
1415 else if (instance->type == PHY_TYPE_PCIE)
1416 pcie_phy_instance_power_off(tphy, instance);
1423 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1426 if (instance->type == PHY_TYPE_USB2)
1427 u2_phy_instance_exit(tphy, instance);
1429 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1435 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1438 if (instance->type == PHY_TYPE_USB2)
1439 u2_phy_instance_set_mode(tphy, instance, mode);
1448 struct mtk_phy_instance *instance = NULL;
1460 instance = tphy->phys[index];
1464 if (!instance) {
1469 instance->type = args->args[0];
1470 if (!(instance->type == PHY_TYPE_USB2 ||
1471 instance->type == PHY_TYPE_USB3 ||
1472 instance->type == PHY_TYPE_PCIE ||
1473 instance->type == PHY_TYPE_SATA ||
1474 instance->type == PHY_TYPE_SGMII)) {
1475 dev_err(dev, "unsupported device type: %d\n", instance->type);
1481 phy_v1_banks_init(tphy, instance);
1485 phy_v2_banks_init(tphy, instance);
1492 ret = phy_efuse_get(tphy, instance);
1496 phy_parse_property(tphy, instance);
1497 phy_type_set(instance);
1498 phy_debugfs_init(instance);
1500 return instance->phy;
1602 struct mtk_phy_instance *instance;
1607 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1608 if (!instance) {
1613 tphy->phys[port] = instance;
1630 instance->port_base = devm_ioremap_resource(subdev, &res);
1631 if (IS_ERR(instance->port_base)) {
1632 retval = PTR_ERR(instance->port_base);
1636 instance->phy = phy;
1637 instance->index = port;
1638 phy_set_drvdata(phy, instance);
1641 clks = instance->clks;
1648 retval = phy_type_syscon_get(instance, child_np);