Lines Matching defs:base
125 void __iomem *base = mipi_tx->regs;
155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON,
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON,
173 mtk_phy_set_bits(base + MIPITX_DSI_CON,
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,
180 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
182 mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0,
197 writel(pcw, base + MIPITX_DSI_PLL_CON2);
199 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN);
201 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
205 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN);
207 mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP,
217 void __iomem *base = mipi_tx->regs;
221 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
223 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE);
225 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,
229 mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN);
231 mtk_phy_clear_bits(base + MIPITX_DSI_CON,
234 mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON,
237 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK);