Lines Matching refs:hdmi_phy
20 static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)
23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);
27 mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable)
29 void __iomem *regs = hdmi_phy->regs;
31 mtk_hdmi_ana_fifo_en(hdmi_phy);
44 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
45 void __iomem *regs = hdmi_phy->regs;
56 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
57 void __iomem *regs = hdmi_phy->regs;
89 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
90 void __iomem *regs = hdmi_phy->regs;
209 static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
225 hdmi_phy->tmds_over_340M = true;
227 hdmi_phy->tmds_over_340M = false;
302 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
303 void __iomem *regs = hdmi_phy->regs;
307 u32 pixel_clk = hdmi_phy->pll_rate;
359 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
360 void __iomem *regs = hdmi_phy->regs;
393 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
394 void __iomem *regs = hdmi_phy->regs;
411 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
413 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,
416 return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate);
422 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
424 hdmi_phy->pll_rate = rate;
431 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
433 return hdmi_phy->pll_rate;
444 static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on)
446 void __iomem *regs = hdmi_phy->regs;
454 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
456 vtx_signal_en(hdmi_phy, true);
460 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
462 vtx_signal_en(hdmi_phy, false);
468 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
471 ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);
476 mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);