Lines Matching refs:lane
40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
227 unsigned int lane;
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
397 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,
400 if (lane->id == 2) {
401 /* lane 2 PHY registers are accessed indirectly */
402 comphy_set_indirect(lane->priv,
406 void __iomem *base = lane->id == 1 ?
407 lane->priv->lane1_phy_regs :
408 lane->priv->lane0_phy_regs;
415 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,
421 if (lane->id == 2) {
424 /* lane 2 PHY registers are accessed indirectly */
426 lane->priv->lane2_phy_indirect +
429 ret = readl_poll_timeout(lane->priv->lane2_phy_indirect +
434 void __iomem *base = lane->id == 1 ?
435 lane->priv->lane1_phy_regs :
436 lane->priv->lane0_phy_regs;
447 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,
450 comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),
454 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,
460 return readl_poll_timeout(lane->priv->comphy_regs +
461 COMPHY_PHY_REG(lane->id, reg),
468 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)
473 switch (lane->mode) {
476 if (lane->id == 2)
483 if (lane->id == 0)
485 else if (lane->id == 1)
492 if (lane->id == 2)
494 else if (lane->id == 0)
502 if (lane->id == 1)
512 spin_lock_irqsave(&lane->priv->lock, flags);
514 old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
516 writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
518 spin_unlock_irqrestore(&lane->priv->lock, flags);
520 dev_dbg(lane->dev,
522 lane->id, lane->mode, old, new);
526 dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id,
527 lane->mode);
532 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)
538 ret = mvebu_a3700_comphy_set_phy_selector(lane);
543 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
548 if (lane->invert_tx)
550 if (lane->invert_rx)
553 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
556 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
560 if (lane->priv->xtal_is_40m)
567 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
570 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
574 comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,
590 ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,
594 dev_err(lane->dev, "Failed to lock SATA PLL\n");
599 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
623 comphy_lane_reg_set(lane, addr, val, 0xFFFF);
628 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)
634 ret = mvebu_a3700_comphy_set_phy_selector(lane);
647 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
652 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
658 switch (lane->submode) {
670 dev_err(lane->dev,
671 "unsupported phy speed %d on comphy lane%d\n",
672 lane->submode, lane->id);
677 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
688 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
696 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
702 if (lane->priv->xtal_is_40m)
708 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
724 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);
743 dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n",
744 lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G");
745 if (lane->priv->xtal_is_40m)
746 comphy_gbe_phy_init(lane,
747 lane->submode != PHY_INTERFACE_MODE_2500BASEX);
753 if (lane->invert_tx)
755 if (lane->invert_rx)
758 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
768 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
774 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
779 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
780 lane->id);
787 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);
796 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1,
799 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
804 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
805 lane->id);
809 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
813 dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n",
814 lane->id);
820 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)
826 ret = mvebu_a3700_comphy_set_phy_selector(lane);
831 comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
844 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);
856 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);
861 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,
866 * Use margining signals from lane configuration
868 comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,
878 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);
883 comphy_lane_reg_set(lane, COMPHY_GEN2_SET2,
893 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);
899 if (lane->priv->xtal_is_40m) {
912 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
917 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
922 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
928 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);
933 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
941 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);
947 if (lane->invert_tx)
949 if (lane->invert_rx)
952 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
957 comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,
963 comphy_lane_reg_set(lane, COMPHY_GEN2_SET3,
971 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
976 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
979 dev_err(lane->dev, "Failed to lock USB3 PLL\n");
985 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)
991 ret = mvebu_a3700_comphy_set_phy_selector(lane);
996 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,
1000 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,
1004 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,
1011 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1014 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
1020 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
1032 if (lane->priv->xtal_is_40m)
1040 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1043 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
1049 if (lane->invert_tx)
1051 if (lane->invert_rx)
1054 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1059 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1064 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
1067 dev_err(lane->dev, "Failed to lock PCIE PLL\n");
1073 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)
1076 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
1080 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1085 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)
1092 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
1096 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)
1099 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1103 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
1111 static bool mvebu_a3700_comphy_check_mode(int lane,
1122 if (mvebu_a3700_comphy_modes[i].lane == lane &&
1137 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1139 if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {
1140 dev_err(lane->dev, "invalid COMPHY mode\n");
1146 (lane->mode != mode || lane->submode != submode))
1150 lane->mode = mode;
1151 lane->submode = submode;
1158 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1160 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,
1161 lane->submode)) {
1162 dev_err(lane->dev, "invalid COMPHY mode\n");
1166 switch (lane->mode) {
1168 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
1169 return mvebu_a3700_comphy_usb3_power_on(lane);
1171 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
1172 return mvebu_a3700_comphy_sata_power_on(lane);
1174 dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id);
1175 return mvebu_a3700_comphy_ethernet_power_on(lane);
1177 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
1178 return mvebu_a3700_comphy_pcie_power_on(lane);
1180 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
1187 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1189 switch (lane->id) {
1191 mvebu_a3700_comphy_usb3_power_off(lane);
1192 mvebu_a3700_comphy_ethernet_power_off(lane);
1195 mvebu_a3700_comphy_pcie_power_off(lane);
1196 mvebu_a3700_comphy_ethernet_power_off(lane);
1199 mvebu_a3700_comphy_usb3_power_off(lane);
1200 mvebu_a3700_comphy_sata_power_off(lane);
1203 dev_err(lane->dev, "invalid COMPHY mode\n");
1218 struct mvebu_a3700_comphy_lane *lane;
1226 lane = phy_get_drvdata(phy);
1229 if (port != 0 && (port != 1 || lane->id != 0)) {
1230 dev_err(lane->dev, "invalid port number %u\n", port);
1234 lane->invert_tx = args->args[1] & BIT(0);
1235 lane->invert_rx = args->args[1] & BIT(1);
1305 struct mvebu_a3700_comphy_lane *lane;
1322 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
1323 if (!lane) {
1335 lane->priv = priv;
1336 lane->dev = &pdev->dev;
1337 lane->mode = PHY_MODE_INVALID;
1338 lane->submode = PHY_INTERFACE_MODE_NA;
1339 lane->id = lane_id;
1340 lane->invert_tx = false;
1341 lane->invert_rx = false;
1342 phy_set_drvdata(phy, lane);