Lines Matching refs:data
285 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
298 /* 40M1G25 mode init data */
369 static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)
374 val = (val & ~mask) | (data & mask);
378 static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
383 val = (val & ~mask) | (data & mask);
389 u32 offset, u16 data, u16 mask)
394 data, mask);
398 u16 reg, u16 data, u16 mask)
404 data, mask);
411 data, mask);
422 u32 data;
431 data, (data & bits) == bits,
437 u16 data;
440 data, (data & bits) == bits,
448 u8 reg, u32 data, u32 mask)
451 data, mask);
458 u32 data;
462 data, (data & bits) == bits,
534 u32 mask, data, ref_clk;
547 data = 0x0;
549 data |= TXD_INVERT_BIT;
551 data |= RXD_INVERT_BIT;
553 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
555 /* 1. Select 40-bit data width */
565 data = ref_clk | COMPHY_MODE_SATA;
567 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
630 u32 mask, data, speed_sel;
644 data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
645 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
647 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
650 data = 0x0;
652 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
675 data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel);
677 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
686 data = COMPHY_MODE_SERDES;
688 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
694 data = 0x0;
696 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
703 data = REF_FREF_SEL_SERDES_50MHZ;
705 data = REF_FREF_SEL_SERDES_25MHZ;
708 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
719 * 11. Program COMPHY register SEL_BITS to set correct parallel data
722 data = DATA_WIDTH_10BIT;
724 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);
752 data = 0x0;
754 data |= TXD_INVERT_BIT;
756 data |= RXD_INVERT_BIT;
758 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
766 data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
767 mask = data;
768 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
790 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
822 u32 mask, data, cfg, ref_clk;
841 data = PRD_TXDEEMPH0_MASK;
844 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);
853 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
856 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);
875 data = 0x0;
878 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);
890 data = GS2_VREG_RXTX_MAS_ISET_60U;
893 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);
907 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
912 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
914 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
917 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
931 * 11. Set 20-bit data width
939 data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT;
941 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);
946 data = 0x0;
948 data |= TXD_INVERT_BIT;
950 data |= RXD_INVERT_BIT;
952 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
969 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
971 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
987 u32 mask, data, ref_clk;
1008 data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT;
1011 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1018 data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN;
1019 mask = data;
1020 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
1037 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1040 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1048 data = 0x0;
1050 data |= TXD_INVERT_BIT;
1052 data |= RXD_INVERT_BIT;
1054 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1057 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
1058 mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;
1059 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1087 u32 mask, data;
1089 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT |
1091 mask = data;
1092 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);