Lines Matching defs:mask
369 static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)
374 val = (val & ~mask) | (data & mask);
378 static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
383 val = (val & ~mask) | (data & mask);
389 u32 offset, u16 data, u16 mask)
394 data, mask);
398 u16 reg, u16 data, u16 mask)
404 data, mask);
411 data, mask);
448 u8 reg, u32 data, u32 mask)
451 data, mask);
534 u32 mask, data, ref_clk;
552 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
553 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
566 mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK;
567 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
630 u32 mask, data, speed_sel;
645 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
647 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
651 mask = PIN_RESET_COMPHY_BIT;
652 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
676 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;
677 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
687 mask = COMPHY_MODE_MASK;
688 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
695 mask = PHY_REF_CLK_SEL;
696 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
707 mask = REF_FREF_SEL_MASK;
708 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
723 mask = SEL_DATA_WIDTH_MASK;
724 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);
757 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
758 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
767 mask = data;
768 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
822 u32 mask, data, cfg, ref_clk;
842 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
844 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);
854 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
856 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);
876 mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK |
878 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);
891 mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |
893 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);
909 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
912 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
915 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
917 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
940 mask = 0xFFFF;
941 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);
951 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
952 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
970 mask = 0xFFFF;
971 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
987 u32 mask, data, ref_clk;
1009 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
1011 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1019 mask = data;
1020 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
1039 mask = 0xFFFF;
1040 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1053 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
1054 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1058 mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;
1059 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1087 u32 mask, data;
1091 mask = data;
1092 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);