Lines Matching refs:base

111 	void __iomem *base;
114 static unsigned int u2o_get(void __iomem *base, unsigned int offset)
116 return readl_relaxed(base + offset);
119 static void u2o_set(void __iomem *base, unsigned int offset,
124 reg = readl_relaxed(base + offset);
126 writel_relaxed(reg, base + offset);
127 readl_relaxed(base + offset);
130 static void u2o_clear(void __iomem *base, unsigned int offset,
135 reg = readl_relaxed(base + offset);
137 writel_relaxed(reg, base + offset);
138 readl_relaxed(base + offset);
144 void __iomem *base = mmp3_usb_phy->base;
147 u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
149 u2o_set(base, USB2_PLL_REG0,
153 u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
155 u2o_set(base, USB2_PLL_REG0,
163 u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
167 u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
173 u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
174 u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
176 u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
179 u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
183 u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
184 u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
186 u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
187 u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
189 u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
191 u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
199 void __iomem *base = mmp3_usb_phy->base;
215 u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
217 u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
219 u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
223 while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
257 mmp3_usb_phy->base = devm_platform_ioremap_resource(pdev, 0);
258 if (IS_ERR(mmp3_usb_phy->base)) {
260 return PTR_ERR(mmp3_usb_phy->base);