Lines Matching refs:lane
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable)
61 struct a38x_comphy *priv = lane->priv;
67 conf |= BIT(lane->port);
69 conf &= ~BIT(lane->port);
74 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
79 val = readl_relaxed(lane->base + offset) & ~mask;
80 writel(val | value, lane->base + offset);
83 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
86 a38x_comphy_set_reg(lane, COMPHY_CFG1,
92 static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
98 ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
103 dev_err(lane->priv->dev,
104 "comphy%u: timed out waiting for status\n", lane->n);
115 struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
136 a38x_set_conf(lane, false);
138 a38x_comphy_set_speed(lane, gen, gen);
140 ret = a38x_comphy_poll(lane, COMPHY_STAT1,
147 a38x_set_conf(lane, true);
160 struct a38x_comphy_lane *lane;
171 lane = phy_get_drvdata(phy);
172 if (lane->port >= 0)
175 lane->port = args->args[0];
177 val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
178 val = (val >> (4 * lane->n)) & 0xf;
180 if (!gbe_mux[lane->n][lane->port] ||
181 val != gbe_mux[lane->n][lane->port]) {
182 dev_warn(lane->priv->dev,
183 "comphy%u: not configured for GBE\n", lane->n);
229 if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
240 priv->lane[val].base = base + 0x28 * val;
241 priv->lane[val].priv = priv;
242 priv->lane[val].n = val;
243 priv->lane[val].port = -1;
244 phy_set_drvdata(phy, &priv->lane[val]);