Lines Matching defs:phy_regmap

88 	struct regmap			*phy_regmap;
103 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
106 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
107 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
110 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
111 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
113 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
118 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
121 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
124 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
127 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
131 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
134 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
135 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
138 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
145 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
148 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
151 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
155 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
159 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
163 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
167 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
169 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
175 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
176 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
177 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
178 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
187 	ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
220 		regmap_update_bits(priv->phy_regmap, slices[i].reg,
226 		regmap_update_bits(priv->phy_regmap, slices[i].reg,
232 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
233 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
234 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
236 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
239 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
240 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
241 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
243 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
416 	priv->phy_regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
417 	if (IS_ERR(priv->phy_regmap))
418 		return PTR_ERR(priv->phy_regmap);