Lines Matching refs:phy
3 * PCIe phy driver for Kirin 970
25 #include <linux/phy/phy.h>
168 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
171 writel(val, phy->base + APB_PHY_START_ADDR + reg);
174 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
176 return readl(phy->base + APB_PHY_START_ADDR + reg);
179 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
184 regval = hi3670_apb_phy_readl(phy, reg);
187 hi3670_apb_phy_writel(phy, regval, reg);
190 static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
193 writel(val, phy->base + reg);
196 static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
199 return readl(phy->base + reg);
202 static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
206 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
212 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
215 static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
217 struct device *dev = phy->dev;
224 phy->eye_param, NUM_EYEPARAM);
230 phy->eye_param[i] = EYEPARAM_NOCFG;
233 static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
237 val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
239 if (phy->eye_param[1] != EYEPARAM_NOCFG) {
241 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
244 kirin_apb_natural_phy_writel(phy, val,
247 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
249 if (phy->eye_param[2] != EYEPARAM_NOCFG) {
250 val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
254 if (phy->eye_param[3] != EYEPARAM_NOCFG) {
255 val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
259 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
261 val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
262 if (phy->eye_param[0] != EYEPARAM_NOCFG) {
264 val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
267 kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
269 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
270 if (phy->eye_param[4] != EYEPARAM_NOCFG) {
272 val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
275 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
278 static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
283 regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
286 regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
288 regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
291 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
294 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
297 hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
302 hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
306 static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
308 hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
311 hi3670_apb_phy_updatel(phy,
316 hi3670_apb_phy_updatel(phy,
320 hi3670_apb_phy_updatel(phy,
330 hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
334 static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
336 struct device *dev = phy->dev;
342 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
346 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
354 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
357 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
361 hi3670_apb_phy_updatel(phy,
366 hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
374 static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
378 regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
382 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
386 static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
390 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
397 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
400 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
403 static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
407 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
426 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
429 static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
434 regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
437 hi3670_pcie_oe_ctrl(phy, true);
440 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
442 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
445 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
450 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
452 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
455 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
458 hi3670_pcie_oe_ctrl(phy, false);
462 static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
464 struct device *dev = phy->dev;
471 hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
474 hi3670_pcie_pll_init(phy);
476 ret = hi3670_pcie_pll_ctrl(phy, true);
481 hi3670_pcie_hp_debounce_gt(phy, true);
482 hi3670_pcie_phyref_gt(phy, true);
483 hi3670_pcie_ioref_gt(phy, true);
485 ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
494 hi3670_pcie_ioref_gt(phy, false);
495 hi3670_pcie_phyref_gt(phy, false);
496 hi3670_pcie_hp_debounce_gt(phy, false);
498 hi3670_pcie_pll_ctrl(phy, false);
503 static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
505 struct device *dev = phy->dev;
510 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
518 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
524 static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
526 struct device *dev = phy->dev;
537 regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
540 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
548 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
554 static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
557 struct device *dev = phy->dev;
581 phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
582 if (!phy->apb) {
590 static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
597 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
601 ret = clk_prepare_enable(phy->phy_ref_clk);
605 ret = clk_prepare_enable(phy->apb_sys_clk);
609 ret = clk_prepare_enable(phy->apb_phy_clk);
613 ret = clk_prepare_enable(phy->aclk);
617 ret = clk_prepare_enable(phy->aux_clk);
624 clk_disable_unprepare(phy->aux_clk);
626 clk_disable_unprepare(phy->aclk);
628 clk_disable_unprepare(phy->apb_phy_clk);
630 clk_disable_unprepare(phy->apb_sys_clk);
632 clk_disable_unprepare(phy->phy_ref_clk);
637 static int hi3670_pcie_phy_init(struct phy *generic_phy)
639 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
653 ret = hi3670_pcie_get_resources_from_pcie(phy);
660 static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
662 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
666 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
669 hi3670_pcie_phy_oe_enable(phy, true);
671 ret = kirin_pcie_clk_ctrl(phy, true);
676 regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
677 regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
679 regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
682 hi3670_pcie_natural_cfg(phy);
684 ret = hi3670_pcie_allclk_ctrl(phy, true);
689 hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
693 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
695 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
698 ret = is_pipe_clk_stable(phy);
702 hi3670_pcie_set_eyeparam(phy);
704 ret = hi3670_pcie_noc_power(phy, false);
711 kirin_pcie_clk_ctrl(phy, false);
715 static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
717 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
719 hi3670_pcie_phy_oe_enable(phy, false);
721 hi3670_pcie_allclk_ctrl(phy, false);
724 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
728 * kirin_pcie_clk_ctrl(phy, false);
745 static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
751 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
752 if (IS_ERR(phy->crgctrl))
753 return PTR_ERR(phy->crgctrl);
755 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
756 if (IS_ERR(phy->sysctrl))
757 return PTR_ERR(phy->sysctrl);
759 phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
760 if (IS_ERR(phy->pmctrl))
761 return PTR_ERR(phy->pmctrl);
764 phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
765 if (IS_ERR(phy->phy_ref_clk))
766 return PTR_ERR(phy->phy_ref_clk);
768 phy->aux_clk = devm_clk_get(dev, "aux");
769 if (IS_ERR(phy->aux_clk))
770 return PTR_ERR(phy->aux_clk);
772 phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
773 if (IS_ERR(phy->apb_phy_clk))
774 return PTR_ERR(phy->apb_phy_clk);
776 phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
777 if (IS_ERR(phy->apb_sys_clk))
778 return PTR_ERR(phy->apb_sys_clk);
780 phy->aclk = devm_clk_get(dev, "aclk");
781 if (IS_ERR(phy->aclk))
782 return PTR_ERR(phy->aclk);
785 phy->base = devm_platform_ioremap_resource(pdev, 0);
786 if (IS_ERR(phy->base))
787 return PTR_ERR(phy->base);
789 hi3670_pcie_get_eyeparam(phy);
798 struct hi3670_pcie_phy *phy;
799 struct phy *generic_phy;
802 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
803 if (!phy)
806 phy->dev = dev;
808 ret = hi3670_pcie_phy_get_resources(phy, pdev);
818 phy_set_drvdata(generic_phy, phy);
826 .compatible = "hisilicon,hi970-pcie-phy",
842 MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");