Lines Matching refs:lane
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
45 /* Per SerDes lane registers */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
74 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
81 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
91 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
93 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
94 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
95 #define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
97 #define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
99 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
104 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
135 struct lynx_28g_lane lane[LYNX_28G_NUM_LANE];
152 #define lynx_28g_lane_rmw(lane, reg, val, mask) \
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
155 #define lynx_28g_lane_read(lane, reg) \
156 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
194 static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
204 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK);
205 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK);
215 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK);
216 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK);
227 static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
231 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK);
232 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK);
234 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK);
235 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK);
239 static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
241 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
242 struct lynx_28g_priv *priv = lane->priv;
245 switch (lane->interface) {
262 static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
264 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
265 struct lynx_28g_priv *priv = lane->priv;
268 lynx_28g_cleanup_lane(lane);
270 /* Setup the lane to run in SGMII */
276 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK);
277 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK);
281 lynx_28g_lane_set_pll(lane, pll);
283 /* Choose the portion of clock net to be used on this lane */
284 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
287 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
290 iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
291 iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
292 iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
293 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
294 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
295 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
298 static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
300 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
301 struct lynx_28g_priv *priv = lane->priv;
304 lynx_28g_cleanup_lane(lane);
306 /* Enable the SXGMII lane */
312 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK);
313 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK);
317 lynx_28g_lane_set_pll(lane, pll);
319 /* Choose the portion of clock net to be used on this lane */
320 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
323 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
326 iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
327 iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
328 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
329 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
330 iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
331 iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
336 struct lynx_28g_lane *lane = phy_get_drvdata(phy);
339 if (!lane->powered_up)
343 lynx_28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ);
344 lynx_28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ);
348 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
349 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
353 lane->powered_up = false;
360 struct lynx_28g_lane *lane = phy_get_drvdata(phy);
363 if (lane->powered_up)
366 /* Issue a reset request on the lane */
367 lynx_28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ);
368 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
372 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
373 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
377 lane->powered_up = true;
384 struct lynx_28g_lane *lane = phy_get_drvdata(phy);
385 struct lynx_28g_priv *priv = lane->priv;
386 int powered_up = lane->powered_up;
392 if (lane->interface == PHY_INTERFACE_MODE_NA)
398 /* If the lane is powered up, put the lane into the halt state while
409 lynx_28g_lane_set_sgmii(lane);
412 lynx_28g_lane_set_10gbaser(lane);
419 lane->interface = submode;
424 /* Power up the lane if necessary */
434 struct lynx_28g_lane *lane = phy_get_drvdata(phy);
435 struct lynx_28g_priv *priv = lane->priv;
448 struct lynx_28g_lane *lane = phy_get_drvdata(phy);
450 /* Mark the fact that the lane was init */
451 lane->init = true;
453 /* SerDes lanes are powered on at boot time. Any lane that is managed
457 lane->powered_up = true;
512 struct lynx_28g_lane *lane;
517 lane = &priv->lane[i];
519 mutex_lock(&lane->phy->mutex);
521 if (!lane->init || !lane->powered_up) {
522 mutex_unlock(&lane->phy->mutex);
526 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
528 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
530 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
534 mutex_unlock(&lane->phy->mutex);
540 static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
544 pss = lynx_28g_lane_read(lane, LNaPSS);
548 lane->interface = PHY_INTERFACE_MODE_SGMII;
551 lane->interface = PHY_INTERFACE_MODE_10GBASER;
554 lane->interface = PHY_INTERFACE_MODE_NA;
567 return priv->lane[idx].phy;
589 struct lynx_28g_lane *lane = &priv->lane[i];
592 memset(lane, 0, sizeof(*lane));
598 lane->priv = priv;
599 lane->phy = phy;
600 lane->id = i;
601 phy_set_drvdata(phy, lane);
602 lynx_28g_lane_read_configuration(lane);